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ECE 224a CMOS VLSI Design Lab

ECE 224a CMOS VLSI Design Lab. F. Brewer. ECE 224a. Fabricate a real design MMI/Cadence/Mentor/Synopsys Tools MMI Full Custom (Cell, Array, Data-Path) Cadence/Synopsys P&R (digital path) Not a first class in VLSI 124a or equivalent required, 124d is good plan Review Essential Concepts

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ECE 224a CMOS VLSI Design Lab

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  1. ECE 224a CMOS VLSI Design Lab F. Brewer

  2. ECE 224a • Fabricate a real design • MMI/Cadence/Mentor/Synopsys Tools • MMI Full Custom (Cell, Array, Data-Path) • Cadence/Synopsys P&R (digital path) • Not a first class in VLSI • 124a or equivalent required, 124d is good plan • Review Essential Concepts • FET, Diode, Transient Model (Elmore), Sizing • Layout/Design Rules: Wire Planning, Gradient Variation, Tricks of Trade

  3. Class Logistics • Homework (out wed, due 1 week) • Quizzes (3 in-class) • No Final • Design Proposal • Design Review • Submitted Project Report

  4. The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966

  5. Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation

  6. ECE224a Project • 0.6um 3M • 3.3-5V bulk CMOS • P1/P2 CAP • Poly Resistor • HV Implants (up to 40V!) • 2.25mm2 • 1.5mmx1.5mm • 9 week design cycle, 3 person

  7. Current State of Affairs • High-End Technology (32-22nm) still a driver • Limited to large design efforts ($$$NRE) • Small number of Players • FPGA: Actel, Lattice, Xilinx, Altera • Processor: AMD, Intel, IBM • SOC: Conexant, Cisco, Juniper, Nintendo… • Structured ASIC: NEC, Fujitsu, Hitatchi, Samsung • Most Design Starts > 0.09um! • Mixed Signal Applications • Mature Technology – Lower NRE and Risk • High Potential for Innovative Design/Architecture

  8. 224a Project Limits • Get 1 1.5x1.5mm design/2-3 students • 1500 Standard Cell Gates • 50kbits ROM/5kbits SRAM • 64 Comparators/ 15 Op-Amps • 40-48 pins (at least 8 used for Pwr/Gnd) • 100Mhz practical large swing (3.3V) limit • 800+MHz differential 300mV • 3.3 or 5V default, 12V possible

  9. Design Schedule • 9 week design flow • 1 week project definition • 3 weeks schematic/simulation + test design • 2 weeks layout • 2 weeks design verification and tweak • Tape Out • Must be DRC, LVS Clean • Must have Full Die Simulation/Sanity • Must have test plan and agree to physical test

  10. Survival Guide • Choose Team to Complement Skills! • No more than 3. 2 is fine, 1 if enough project slots • Under-Specify/Over-Deliver • If you cannot finish basic design in 1 week simplify design! • Basic Design through layout before adding features! • Make decisions early, stick to them • Use expert resources: Professors, experienced students • Goal: Have Fun! --

  11. What to make? • Mixed Signal Designs Rock • Pure Digital 1-bit signal processing • Analog Sensors/Digital Output Good Choice • Temperature, Light, Magnetic, RF, Field, voltage, current, time, phase… • Digital Synthesis/Power also good • Sound (even music!), RFID/Xmit, motor driver/controller, PLL (clock synthesis or other…), Display (LCD) or LED • Tricky Small Designs • Journal of Consumer Circuits, JSSC about 10-15 years ago (0.5um in vogue), LFSR tricks…

  12. What to NOT make: • MicroProcessor • 4-bit possible (8 bit tiny MIPS – won’t fit w/o reg) • 1 success in 22 years, 5 months design time • No non-volatile Memory • (design some is good, but hard, project!) • Digital Multiplier/Adder/Function Block • Space, Pins (How to test!), Why? • Generic OpAmp • How to test/characterize? • If you have a use in mind – it is not generic!

  13. Design Methodology

  14. Evolution in Complexity

  15. 100,000,000 10,000,000 1,000,000 10,000,000 100,000 58%/Yr. compound 1,000,000 Complexity growth rate 10,000 100,000 Logic Transistors per Chip (K) Productivity (Trans./Staff-Month) 10,000 1,000 100 1,000 Productivity growth rate 10 100 21%/Yr. compound 1981 1985 1989 1993 1997 2001 2005 2009 The Design Productivity Challenge Logic Transistors per Chip (K) Productivity (Trans./Staff-Month) 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 A growing gap between design complexity and design productivity Source: ITRS’97

  16. Scaling? • Technology shrinks by 0.7/generation • With every generation can integrate 2x more functions per chip; chip cost does not increase significantly • Cost of a function decreases by 2x • But … • How to design chips with more and more functions? • Design engineering population does not double every two years… • Physical design constraints more and more difficult to surmount • Diminishing Returns for Design Dollars

  17. The Custom Approach Intel 4004 Courtesy Intel

  18. Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 80486 Intel 80286 Transition to Automation and Regular Structures Courtesy Intel

  19. Automating Design • Exploitation By Algorithms • Regular Structures • Logic Synthesis • Regularization of Connection • Floorplanning (Localization of function) • System Level Performance/Power/Cost • Allocation of Physical Resources • Communication/Interconnect • Hierarchy based on Sensitivity to Latency • Wires to Link Protocols

  20. A System-on-a-Chip: Example Courtesy: Philips

  21. Design Methodology • Design process traverses iteratively between three abstractions: behavior, structure, and geometry • Trick: automate these steps

  22. Digital Circuit Implementation Approaches Custom Semi-custom Cell-based Array-based Standard Cells Pre-diffused Pre-wired Hard Macros Ma cro Cells Compiled Cells (Gate Arrays) (FPGA's) (RAM/ROM) Implementation Choices

  23. Implementation Strategies • Data-Path • 1D tiling, custom in depth • Cell based logic • Technology confined to cells (area) • 2D via 1D cell rows, automatic P&R • 2D Arrays (Memory, CAM, CCD, MPY) • Dense but very constrained • Design time consuming!

  24. 2-d Cell Based: “Hard” Modules 25632 (or 8192 bit) SRAM Generated by hard-macro module generator

  25. 1-d Cell-based Design (standard cells) Feedthrough cell Logic cell Routing channel Rows of cells Functional Routing channel requirements are reduced by presence of more interconnect layers module (RAM, multiplier, )

  26. Concepts of Placement • Standard cells are placed in “placement rows” • Cells in a timing-critical path are placed close together to reduce routing related delays (Timing Driven) • Placement rows can be abutting or non-abutting

  27. Concepts of Routing • Connecting between metal layers requires one or more “vias” • Metal Layers have preferred routing directions • Metal 1 (Blue) Horizontal • Metal 2 (Yellow) Vertical • Metal 3 (Red) Horizontal

  28. Concept of Routing Tracks • Metal routes must meet minimum width and spacing “design rules” to prevent open and short circuits during fabrication • In grid based routing systems, these design rules determine the minimum center-to-center distance for each metal layer (Track/Grid spacing) • Congestion occurs if there are more wires to be routed than available tracks

  29. Grid-Based Routing System • Metal traces (routes) are built along and centered around routing tracks • Each metal layer has its own tracks and preferred routing direction • Metal 1 – Horizontal • Metal 2 – Vertical • Track and pitch information can be located in the technology file • Design Rules

  30. Standard Cell — Old Example • Automation • Height fixed • Width variable • Channel routing • Optimization • Place by annealing to minimize wire-length and net criticality [Brodersen92]

  31. Standard Cell – The New Generation Cell-structure hidden underinterconnect layers Same basic scheme -- more layers -- wires over cells -- power/clock plan -- leave spaces for Filler/bypass and Buffer cells

  32. Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

  33. “Soft” MacroModules Synopsys DesignCompiler

  34. Gate Array — Sea-of-gates Uncommited Cell Committed Cell(4-input NOR)

  35. Sea-of-gate Primitive Cells Using oxide-isolation Using gate-isolation

  36. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS) Courtesy LSI Logic

  37. The return of gate arrays? Via programmable gate array(VPGA) Via-programmable cross-point metal-6 metal-5 programmable via Exploits regularity of interconnect [Pileggi02]

  38. Pre-wired Arrays: Classification of prewired arrays (or field-programmable devices): • Based on Programming Technique • Fuse-based (program-once) • Non-volatile EPROM based • RAM based • Programmable Logic Style • Array-Based • Look-up Table • Programmable Interconnect Style • Channel-routing • Mesh networks

  39. Fuse-Based FPGA antifuse polysilicon ONO dielectric n antifuse diffusion + 2 l Open by default, closed by applying current pulse From Smith’97

  40. I I I I I I 5 4 3 2 1 0 Programmable I I I I 3 2 1 0 I I I I I I OR array 5 4 3 2 1 0 Fixed AND array O O O O O 3 2 1 0 O 0 0 Indicates programmable connection Indicates fixed connection Array-Based Programmable Logic Programmable OR array Fixed OR array Programmable AND array Programmable AND array O O O O O O 3 2 1 3 2 1 PLA (flexible – sizing) PROM (dense) PAL (uniform load)

  41. 1 X X X 2 1 0 : programmed node NA NA f f 1 0 Programming a PROM

  42. Rent’s Rule • Rent described a relation between the number of components in a subsystem and the number of wires to connect it. • The rule was developed for large digital systems, but is reflected in all human design (hierarchy) • A Rent coefficient of 0.5 corresponds to a planar scalable design – i.e. the perimeter (where wires go) is grows to support the area of a planar figure.

  43. Rent’s Rule: 10,000 board level high performance computers 1,000 gate arrays r=0.5K=1.9 chip level microprocessors r=0.63K=1.4 r=0.45K=0.82 100 r=0.12K=6 static ram dynamic ram 10 100 1,000 10,000 100,000 1,000,000 [Bakoglu, 1987]

  44. Design Flow

  45. Design Flow - Overview • Generic VLSI Design Flow from System Specification to Fabrication and Testing • Steps prior to Circuit/Physical design are part of the FRONT-END flow • Physical Level Design is part of the BACK-END flow • Physical Design is also known as “Place and Route” • CAD tools are involved in all stages of VLSI design flow • Different tools can be used at different stages due to EDA common data formats*

  46. Where does the Gate Level Netlist come from?

  47. Floorplanning • 2D layout: • Area does not correspond to architecture • Communication on boundaries – wire length

  48. Design Must Be Floorplanned Before P&R • Floorplan of design: • Core area defined with large macros placed • Periphery area defined with I/O macros placed • Power and Ground Grid (Rings and Straps) established • Utilization: • Percentage of the core used by placed standard cells and macros typically 80-85%

  49. I/O Placement and Chip Package Requirements • Some Bond Wire requirements: • No Crossing • Minimum Spacing • Maximum Angle • Maximum Length

  50. Guidelines for a Good Floorplan • A few quick iterations of place and route with timing checks may reveal the need for a different floorplan

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