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Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency

Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency. Bo Fu and Paul Ampadu IEEE International Symposium on Circuits and Systems,pp.1173-1176, 27-30 May 2007 指導老師 : 魏凱城 老師 學 生 : 蕭荃泰

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Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency

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  1. Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency Bo Fu and Paul Ampadu IEEE International Symposium on Circuits and Systems,pp.1173-1176, 27-30 May 2007 指導老師: 魏凱城 老師 學 生: 蕭荃泰 日 期: 97年3月3日 彰化師範大學積體電路設計研究所

  2. Outline • Abstract • Flip Flop Design Metrics • Experimental Setup • Simulation Results • Conclusions

  3. Abstract • In this paper, the impact of voltage scaling on the performance of flip-flops is analyzed. • Four representative flip-flops are compared at ultra-low voltages, for delay, energy and energy-delay-product (EDP). • Voltage scaling has become one of the most effective techniques to reduce system energy consumption.

  4. Flip Flop Design Metrics • PowerPC Master-slaver latch 1 0 0 1 0 1 1 0

  5. Modified Clock CMOS (mC2MOS) Master-slave latch 1 0 1 0 0 1 1 0 1 0 1 0 0 1 0 1

  6. Hybrid-latch Flip Flop (HLFF) 0 1 0 1 0 1 1 1 0 1

  7. Sense-Amplifier-based Flip Flop (SAFF) 0 1 1 1 0 0 1 1 1 0 Q改變 Q不變 設=1 0 0 1

  8. Timing parameters Definition of Tsetup

  9. Experimental Setup The simulation test bench.

  10. Simulation Results • Experiments were performed using the 90 nm Predictive Technology Model (PTM) [11] at room temperature (27oC). • The flip-flops are optimized for minimum energy at a nominal supply voltage 1.2 V using the sizing schemes mentioned in [4].

  11. a. Effects of Voltage Scaling onTiming Parameters (a) Function failure voltages (b) Function failure in HLFF Supply voltages of various flip-flop designs failing to latch the proper data

  12. Low-to-high High-to-low Low-to-high High-to-low (a) TC->Q (b) Tsetup Timing parameters of the flip-flop as a function of the supply voltage.

  13. (c) Worst case delay of TD->Q Timing parameters of the flip-flop as a function of the supply voltage.

  14. (a) Supply voltage 1.2 V (b) Supply voltage 0.3 V High-to-low transition of HLFF with a varied TD->C time.

  15. b. Effect of Voltage Scaling on Energy Consumption • The energy dissipation of selected flip-flop designs from 0.3 V to 1.2 V with a clock frequency of 50 MHz. • The result shows that PowerPC consumes the least energy compared to other flip-flops examined.

  16. (b) Activity 0.5 (a) Activity 1 Energy dissipation as a function of the supply voltage for different switching activities.

  17. (c) Activity 0 (all 1) (d) Activity 0 (all 0) Energy dissipation as a function of the supply voltage for different switching activities.

  18. c. Effect of Voltage Scaling on Energy-Delay Product (a) Activity 1 (b) Activity 0 (all 1) EDP as a function of supply voltage and switching activities.

  19. (c) Voltage 1.2 V (d) Voltage 0.3 V EDP as a function of supply voltage and switching activities.

  20. Conclusions • The performance of various flip-flops at ultra-low voltages was analyzed in this paper. • The impact of supply voltage scaling on timing parameters of a flip-flop depends on the type of flip-flop and input transition. • For energy efficient operation at ultra-low voltages, HLFF achieves the smallest EDP when switching activity is high and a transistor based flip-flop achieves the smallest EDP at low switching activities.

  21. THE END

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