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SETNET MEETING - The Cost of Test Thursday 21 February 2002 TUC Congress Centre , London

SETNET MEETING - The Cost of Test Thursday 21 February 2002 TUC Congress Centre , London. Chris Brown Sales Engineer Teradyne Inc. The Cost of Test – What is it?. Direct Costs. Cost of the test system. Cost of the prober or handler.

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SETNET MEETING - The Cost of Test Thursday 21 February 2002 TUC Congress Centre , London

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  1. SETNET MEETING - The Cost of TestThursday 21 February 2002TUC Congress Centre, London Chris Brown Sales Engineer Teradyne Inc.

  2. The Cost of Test – What is it? • Direct Costs. • Cost of the test system. • Cost of the prober or handler. • Cost of support hardware (docking, interface boards, probecards). • Hidden Costs. • Floorspace usage. • Uptime/Downtime (Reliability). • Cost of application support.

  3. Reduce Test Costs Requirements of Semiconductor Manufacturers from an ATE perspective • Performance • Price • Time To Market • Reliability • Productivity • Quality

  4. Example:The ‘non-memory’ -Semiconductor Markets CISC µProcessor RISC µProcessor Graphics Modems Storage PRICE PER PIN Chipsets Embedded Controllers DSPs High Performance Audio/Video PLDs/FPGAs Gate Arrays 16/32-bit µController High Integration (SOC) 8-bit µController High Volume Smart Cards PERFORMANCE

  5. Case 1: Microcontroller Market Range of microcontroller performance and test requirements are constantly expanding RF THROUGHPUT Smartcards 8 Bit A/D - D/A 12 Bit A/D - D/A 8 bit uC EEPROM 16/32 bit uC OTP Flash DRAM PERFORMANCE

  6. Case 1: Microcontroller Market $3.41 • Dropping prices and increasing volumes are pressuring micro controller test organizations to find new solutions • Competing in the micro controller market requires: • 50% reduction in test cost • Double worldwide capacity DEV I CE ASP SH I PMENT S $2.62 7.3 Billion Units 3 Billion Units 1995 2000 1995 2000 Dataquest - 12/00

  7. Case 2: Smart Card Market Millions of USD Source: Dataquest 7/2000 • Device ASP << 1USD

  8. Case 2: Smart Card Market (cont.) • Lowest device cost • Highest production volume

  9. Cost of Test ‘The Cost of Test’ Conclusion • Dropping device prices and increasing production volume causes a strong demand to constantly reduce the cost of test. Production Volume Device Selling Price

  10. Test Cost Reduction Measures from an ATE point of view No. 1: Parallel test

  11. No. 1: Parallel test Efficiency (R = 1- (dt/dn) / Tsingle) T H R O U G H P U T • Analog/ parametrics tested serially • Memory test driven by slowest device • Programming tester one pin at a time Sites Tested In Parallel THROUGHPUT • All parametrics / analog test in parallel • Memory test optimal test times • Programming tester with command per site • Devices tested asynchronously Sites Tested In Parallel

  12. No. 1: Parallel test – Parallel Test Efficiency Dual site parallel test already cuts test costs by 50%

  13. No. 1: Parallel test – Parallel Test Efficiency Parallel test efficiency becomes relevant at higher site counts

  14. No. 1: Parallel test - Summary • Increasing parallel test does mean increasing throughput per tester • Parallel test has its limits based on how efficient a tester can test sites in parallel. • Basic Principle: HW and SW of the ATE instrument needs to be designed from the ground up for parallel test • Per Pin Instruments • Per Site Instruments • Programming per site • Asynchronous pattern control • Production interface designed for parallel test

  15. Test Cost Reduction Measures from an ATE point of view No. 2: Reduce cost of the test system (Low capital cost tester)

  16. No. 2: Reduce cost of the test system • Zero Footprint Design • Take advantage of leading edge technology • High Reliability • Easy to use software • Low capital cost

  17. Test Cost Reduction Measures from an ATE point of view No. 3: Reduce infrastructure costs

  18. Mainframe Tester (3ft x 9ft) Manipulator Testhead Handplug CPU Testhead Probe No. 3: Reduce infrastructure costs 4.57m Floorspace usage of typical Mainframe Tester + Prober 4.26m

  19. Zero Footprint Tester + Prober Reduce test costs through optimized floorspace usage CPU CPU CPU CPU J750 Tester J750 Tester J750 Tester J750 Tester EG Prober EG Prober EG Prober EG Prober No. 3: Reduce infrastructure costs (cont.) 4.57m 4.26m

  20. Conclusion • To continuously help semiconductor manufacturers to reduce ‘The Cost of Test’ is ‘The’ challenge for the ATE industry. • Several actions have been taken by the ATE industry to reduce test costs. • Improve parallel test efficiency. • Provide low capital cost test equipment. • Reduce infrastructure requirements for ATE test equipment (floorspace, cooling, power consumption) through zero footprint designs.

  21. Thank You.

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