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Gary S. Varner University of Hawai , i. Overview
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Gary S. Varner University of Hawai,i Overview A number of options for readout of a pixel sensor for use in a B-Factory environment have been proposed. The performance requirements and demands on concurrent operation differ from those of the readout electronics being developed for the LHC project, as well as future fixed target applications. Considering these architectures, a specific technique, based upon providing maximally parallel signal encoding, has been chosen for initial prototyping tests. Designated XTEST2, this design was optimized for use in reading out thin hybrid detectors (bump-bonded commercial electronics and custom, thin silicon pixel sensors). The use of thin sensors is required to obtain good position resolution for the low momentum tracks of interest in B meson decay. Simulation and prototyping results are presented below. Monolithic versus Hybrid XTEST2A first Belle Pixel Readout Prototype To reduce the minimum pixel size, input capacitance and material, a monolithic detector, such as shown above, is preferred. However, in order to utilize commercial foundries for the deep sub-mm electronics, bump-bonding is the current baseline. Design and Simulation A block diagram of the electronics found within each pixel cell. Upon receipt of an external trigger, a sample is stored on the capacitor shown. A voltage ramp is used to convert this voltage into a 5-bit code. A time constant, RC, is established between the storage capacitor and biasing FET, which sets the integration time. To save power, the comparator is only active during a 40ms encoding period. After which, he 5 bits of ADC information from all pixel cells are multiplexed and driven off chip via a set of high-speed LVDS drivers (not shown), all within 200ms. SPICE simulation results of the performance of a given XTEST2 pixel cell ADC for the case of a linear ramp. Because the ramp voltage value can be an arbitrary function of the Gray-code encoding values, a non-linear ramp may be used to maximize the input dynamic range. Simulation results of the noise (Equiv. Noise Charge) versus integral time t, with each of the noise components shown. Results shown are for a 100mm detector, after 2MRad dose. Optimization of the Signal to Noise Ratio (SNR) by adjusting t for each of 3 likely Belle trigger conditions. Again, results shown are for a 100mm detector, after 2MRad dose. Prototype Fabrication Radiation test structures 20mm bump pads 100 mm 50 mm A Low Voltage Differential Signal (LVDS) Output driver. 16x24 Array 5-bit Gray-code Counter Detailed view of the layout of a single pixel cell (metal2,3 not shown for clarity). Each cell contains 36 transistors, most of which are minimum size. 90mm2 wire bond pads Photograph of XTEST2 fabricated in the HP0.5mm process during the spring of 2000. The die is dominated by the 84 wire-bonding pads around the periphery and approximately 2.5mm on each side. Summary/Future Plans Initial prototyping of the XTEST2 chip has been successful in demonstrating the radiation hardness and good analog performance of components of the basic design. Unfortunately, due to wiring mistakes in the final artwork, errors precluded testing the encoding and LVDS output. These problems have been fixed and another version, XTEST2A was submitted and should be available for testing in November, 2000. While the radiation hardness of the HP0.5mm process may be adequate, the design rules preclude reducing the pixel size to 40mm x 60mm, an eventual goal. Therefore, in the future it is envisioned to migrate to the TSMC0.25mm process, recently available through the MOSIS multi-project wafer service. Testing Results 160uA A diagram showing the dominant radiation damage effect in the B-Factory environment: the shift in threshold voltage values due to charge trapping. Measurement of threshold voltage shift versus radiation dose, indicating survival to >10MRad. Adjustment range for the R of the RC combination. 5M is the nominal value, which is easily obtained.
Overview • XTEST2A Status • In Fab. @ HP, due back 11/10 • LCPIX0 Design • LCPIX0 design parameters • LCPIX0 proposed architecture • Pre-amp performance • Comparator choice and performance • Hit time encoding • Performance simulations • Summary of performance • Remaining design work • HP0.5um • Oct. 2, Nov. 6
XTEST2 Radiation Results • Radiation hardness consistent with Tox • Quite adequate total dose performance
XTEST2 Initial Prototype Gray-code Counter 16x24 Array of pixels: LVDS Drivers 100 mm Rad-test structures 50 mm
Problems 2: LVDS Driver No connect • HS LVDS test circuit also showed dynamic FF • unexpected behavior, required redesign • no obvious problems with LVDS driver itself
XTEST2 Performance Results Successes: 2 key analog issues comparator works radiation tolerance Failures: GCC + LVDS nENC logic DRC/LVS Redesigns: better power distrib. D-FF, dynamic FFs replaced probe pads cleaned up wiring
Pair Monitor Specifications • Pixel rather than strip (occupancy) • Fast collection time --> 3D Pixel • Trapezoidal geometry • Radiation hard • Conceptual Design Parameters:
Simulation Input Previous simulation results: • Reduction of drift time - model for SPICE input? • Range/spread of amplitudes/risetimes for TWC?
LCPIX0 Footprint Design LCPIX0 to match sensor currently being fabbed: 1.6 mm 5 mm Required size only slightly larger than min. allowed: • ~8 mm2 • no need for complete pad ring (control/readout much simpler)
Readout Electronics progress Gaining experience in design/test of XTEST2, a pixel upgrade effort: Constraints: • Smallest pixel • thin sensor • low power • Many common aspects of designs
Belle Vertexing Upgrade • To improve vertexing • reduce radius • rad hard, high occupancy, thin
XTEST2 Design Concept • Simple readout structure • Decent performance w/o pre-amp (see below) • Comparator powering during encoding • 5-bit Wilkenson encoding (1mV/ms ~ 40ms) • After encoding, fast LVDS data transfer out
Expected Performance • Results for 100mm thick
Interconnect Concerns • Excellent SNR and Timing • However, interconnect issues:
LCPIX0 Design • Specifications: • BX timing possibility • TWC implementations • Encoding Options: • analog ramp • TDC • 1-2ns resolution • LCPIX0: • Submit in 3 months • same process as XTEST2 • proto chips early ‘01
Bump Bonding Tests • Global tender: • only 2 companies willing to work with thin devices: • AIT (Hong Kong) • GEC-Marconi (U.K.) • GEC withdrew ARO • Concern for LHC community also • Bonded both 300mm and 100mm thick devices
Bump Bonding Results (1) • Sample measurement:
Bump bonding Summary • Problems encountered with 50x100mm misalignment Loose Indium? Bad UBM? • Probably no problem for 100x100mm • We continue to seek other solutions
Thinning (after bonding) Utilize Xe-F etcher to thin If can protect the sides (e.g. with photoresist), metal/others OK Initial tests leave room for improvement in uniformity, but solutions being sought:
Despite some problems with uniformity Allows bump-bonding of thick devices Can thin electronics extremely thin uniformity problems may have easy solution Thinning Summary
Summary • R&D into technologies proceeding well: • Have established Rad. Hard processes for both sensor and readout electronics • Developing experience at handling interconnect issues • Plans • Sensor prototype available in 2-3 months • Readout electronics prototype design submission in 2-3 months, prototypes ~3 months thereafter • first prototype system mid next year
LC Interation Region Few x105 e+e- pairs/Bunch crossing
Enabling Technologies: MEMS • Micro-Electro-Mech Structures
Detector Development Reduction of distance between electrodes: • Reduction of drift time • Reduction of depletion voltage 300mm 100mm
Detector Results - sensitivity • Slow amp. readout • Excellent resolution • Energy deposition largely contained within a single drift cell • though electrodes of finite extent, efficient Q acq.
Detector Results - Leakage Current • Excellent performance at “LHC” doses: • Respectable plateau at tolerable leakage current • comparable ATLAS planar sensor difficult to deplete with 600V