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Design of benchmark circuit s5378 for reduced scan mode activity

Nelson Sunwoo. Design of benchmark circuit s5378 for reduced scan mode activity. objective. Modify s5378 to full scan design Modify scan flip flops to prevent switching in combination logic Compare average power consumption of original and enhanced design. Problem with testing.

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Design of benchmark circuit s5378 for reduced scan mode activity

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  1. Nelson Sunwoo Design of benchmark circuit s5378 for reduced scan mode activity

  2. objective • Modify s5378 to full scan design • Modify scan flip flops to prevent switching in combination logic • Compare average power consumption of original and enhanced design

  3. Problem with testing • Scan shift causes redundant switching in combination logic. • Power dissipation during the test mode is up to three times higher than normal mode.

  4. Primary inputs Combinational logic Primary outputs SO D 0 1 DFF mux Q SI Scan flip- flops D SO SE Scan flip-flop Q SI SE Original circuit Scan Flip Flop Scan flip- flops Scan flip- flops . . .

  5. Original circuit simulation

  6. Modified circuit

  7. Modified circuit simulation

  8. Power analysis technology: TSMC 0.18umVdd: 1.8Vclock speed: 1GHz1000 random vector sets - inputs (0.5 activity) - Scan in (random)

  9. simulation

  10. result

  11. reference S. Gerstendrfer and H. J. Wunderlich, Minimized Power Consumption for Scan-based BIST, International Test Conference, 1999, pp 77-84.

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