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Design of Digital-to-Analog Converter

Explore the basics and advanced techniques in designing digital-to-analog converters for control of analog devices. Learn about types like weighted-resistor, R-2R ladder, and current-switched DACs, with insights on glitches and minimizing effects in DAC output voltages.

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Design of Digital-to-Analog Converter

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  1. Design of Digital-to-Analog Converter EE597G Presentation: Qin Chen Yong Wang Dept. of Electrical Engineering Feb. 6th, 2006

  2. What’s DAC? Object • A device that converts digital signals to analog signals • It’s usually used to control analog devices, such as actuator, audio and video output. Object Digital System A/D D/A Ctrl Smpl

  3. Weighted-Resistor DAC – VOUT is a weighted sum of V3, …, V0 with weights proportional to the conductances G3, .., G0. – If X3:0 is a binary number we want conductances in the ratio 8:4:2:1. –Fast: gate slew rate ≈ 3 V/ns. – We can scale the resistors to give the output impedance we want. – Not good for many bits DAC

  4. R-2R Ladder • resistances of the two branches at V1 both equal 2R so the current into this node will split evenly. • using only two resistor values, can generate a whole series of currents where In=2nI0. • From the voltage drop across the • horizontal resistors, we see that • Vn= 2RIn = 2n+1RI0 . For an N-bit ladder the input voltage is therefore I0=2–NVin/R.

  5. Current-Switched DAC • Total current into summing junction is X3:0 ×I0, Vout= X3:0 × Vin /16R× (–Rf) • Use CMOS transmission gates as switches: adjust ladder resistors to account for switch resistance. • All the switch output terminals are at 0 V. Ladder outputs are always connected either to ground or to a virtual earth. Advantages: • Very fast, No need to charge/discharge node capacitances • Only two value resistors can satisfy many bits DAC

  6. Glitches in DAC output voltages • Switches in DAC operate at different speeds ⇒ output glitches occur when several input bits change together: 0111->1000 • Glitches are very noticeable on a video display:

  7. Deglitching with sample/hold circuit • To minimize the effect of glitches: – Use a register to make inputs change as simultaneously as possible – Use a sample/hold circuit to disconnect the DAC output while it is changing

  8. Chip Specifications • Resolution: 8 bits • No. of channels: 2 • Interface: Parallel • Output type: Voltage • Reference: External • Supply voltage: Single, 5V

  9. Chip Specifications (cont.) • Power consumption (Max. 200mW) • Update rate (100MHz) • Settling time (10μs) • Area (1mm2) • Integral Nonlinearity ( 1 LSB) • Differential Nonlinearity (1 LSB)

  10. - - + + Chip Diagram Input Latch A DAC A Out A Input(8 bit) Input Latch B DAC B Out B Address Control Reference Address

  11. Project Schedule

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