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Design and Analysis of A Novel 8T SRAM Cell

Design and Analysis of A Novel 8T SRAM Cell. Department of Microelectronic Engineering & Centre for Efficiency Oriented Languages University College Cork, Ireland & Synopsys, Ireland Jiaoyan Chen , Dilip Vasudevan, Emanuel Popovici, Michel Schellekens, Peter Gillen Email: chenj@ue.ucc.ie.

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Design and Analysis of A Novel 8T SRAM Cell

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  1. Design and Analysis of A Novel 8T SRAM Cell Department of Microelectronic Engineering & Centre for Efficiency Oriented Languages University College Cork, Ireland & Synopsys, Ireland Jiaoyan Chen, Dilip Vasudevan, Emanuel Popovici, Michel Schellekens, Peter Gillen Email: chenj@ue.ucc.ie December 14, 2010

  2. Contents Motivation Architectures of 6T SRAM, 9T SRAM and our 8T SRAM Adiabatic and Non-Adiabatic Operations SNM Comparison Dynamic Power Static Power Conclusion

  3. Motivation SOC Consumer Stationary Power Consumption (2008) Roadmap –Cell Area Trend(ITRS 2008) SRAM consumes a lot of power and area in chips. Our aim is to built an efficient SRAM. Consumer Portable Power Consumption Trend (ITRS 2008 update)

  4. Conventional 6T SRAM Technology: 90nm,65nm,45nm, 28nm… Stability: Static Noise Margin (SNM) is getting Down. Leakage Power: a) Subthreshold leakage current b) Gate oxide leakage current 4

  5. 9T SRAM Features: a) 2 sub-circuits: Upper : Writing Lower: Reading b) Minimal Sizing for the upper part c) SNM is much better d) Lower leakage Power (in super cut-off mode) Z. Liu and V. Kursun, “Characterization of a novel nine-transistor sram cell,” IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 4, pp. 488–492, 2008 5

  6. Proposed 8T SRAM Features: a) 2 sub-circuits: Upper :1. No GND Connection 2. Add One Sharing transistor Lower: Using PMOS b) Half swing BL and BL’ return to VDD/2 after writing or reading. 6

  7. Adiabatic Operations: Writing PMOS P3 is used to meet the Adiabatic Principle: No voltage difference before the transistor turns on

  8. Adiabatic Operations: Reading

  9. Simulation Waveforms

  10. SNM Comparison (45nm) Proposed 8T SRAM Conventional 6T SRAM

  11. Dynamic Power Comparison (1) 8*8 Array 1 Bit Cell

  12. Dynamic Power Comparison (2) 67% 62%

  13. Leakage Power Analysis

  14. Temperature Variation >90%

  15. Process Variation (65nm) – TOX, VTH, U0 >90%

  16. Process Variation (45nm) – TOX, VTH, U0 90%

  17. Conclusion • Summary • Efficient 8T SRAM architecture • Improved SNM compared with 6T SRAM • Very Low Dynamic and Leakage power • Future work • Use 36nm, 28nm…Check performance particularly for leakeage • Further Enhance the Stability • Fabricate and validate the proposed architecture

  18. Thank You Questions?

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