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Status and perspectives for the WP1 project IC technology and IPs

Status and perspectives for the WP1 project IC technology and IPs. K. Kloukinas , A . Marchioro March 2010. Outline. Activities in: Technology, MPW and Tools IP Macro Cells Training and Documentation Plans. Human resources. People involved ( at various percentage levels):

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Status and perspectives for the WP1 project IC technology and IPs

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  1. Status and perspectives for theWP1 projectIC technology and IPs K. Kloukinas, A. Marchioro March 2010

  2. Outline • Activities in: • Technology, MPW and Tools • IP Macro Cells • Training and Documentation • Plans A. Marchioro - March '10

  3. Human resources • People involved ( at various percentage levels): • K. Kloukinas, W. Bialas, S. Bonacini, K.Poltorak, C. Paillard, B. van Koningsveld, P. Moreira, A. Marchioro • Tools, MPWs and technology • 1.2 FTE • 1 person for IT support (including section support) • IP Blocks • 2 FTE A. Marchioro - March '10

  4. Overview of Technologies • Major design support service contract established for CERN and HEP labs • CERN design Kit distributed to 25 Institutes for 130 nm and 5 for 90 nm. • Major milestone: Common methodology and design flow with customized tools outsourced in 2009 for 130nm • To be ported to 90nm in Q2 2010 • To be extended to 65 nm in Q4 2010 CMOS 8RF-DM “Standard” 130 nm Analog & RF designs BiCMOS8WL and 8HPBipolar SiGe device requested by Atlas CMOS 9SF LP/RF High performance technology for dense designs CMOS 10 State of the art CMOS for GBT10G, high density pixels etc 130nm CMOS 90nm CMOS 65nm CMOS Available in 2009 From 2010 A. Marchioro - March '10

  5. Prototyping activity 2008 - 2009 • CMOS8RF (130nm) • 20 designs on 5 MPW runs • 7 runs organized • 2 to 8 designs per MPW run from HEP community • Smallest design 1 mm2, largest design 20 mm2 • 13 designs on 8RF-DM and 7 designs on 8RF-LM • 100 mm2 total silicon area in 2009 • Full CERN 130nm MPW scheduled for May ‘10 • CMOS8WL (130nm SiGe) • 3 designs on 1 MPW run • 10 mm2 total silicon area • CMOS9LP/RF (90nm) • 1 design of 4mm2 on 2009 MPW • Major 90nm run in February ’10, including various SEU and analog test structures (submitted designs) A. Marchioro - March '10

  6. Projects supported • Medipix + Timepix2 + DosePix, all 130nm • Common: • GBT (3 chips), SCA • Technology evaluation 90 nm ST and IBM for all • CMS • New Tracker FE chip: CBC 130nm (IC + RAL) • 3T chip in 250 nm for CMS trigger modules (CERN) • Atlas • FEI4 pixel FE (LBL, Genova, etc.) • Tracker FE ABCN in 130 nm (CERN, U Geneva, Krakow) • Various 130nm SiGe designs for Santa Cruz and UPenn • NA62 • GTK: CERN and Torino versions in 130 nm • LHC machine: • BLM chip (250nm) • External and others: • SAltro 130 nm digital design TPC/Eudet • Bonn: XFEL FE design • RAL: 130nm MAPS design • MPI Munich, 90 nm for 3D pixel • Marseille, 130nm A. Marchioro - March '10

  7. Project: SCA - Slow Control Adapter • Objective: harmonize approach to embedded slow control systems in experiments • Second generation of CCU system in CMS (used in most CMS sub-detectors) • Tailored to GBT based system • Flexible enough to satisfy requirements from most experiments SCA 16xI2C buses JTAG master Slow Control e-link Single Wire bus * Network Controller RXDATA e-port TXDATA ParallelI/O Ports 32 Memory Bus TEMP (2x) ADC8-16 inputs DAC ALARMs A. Marchioro - March '10

  8. LePIX:monolithicsensor inadvancedCMOS • Aim: • Integrate small pixel fast sensor and read-out electronics in same substrate • Reduce substantially power consumption • Possible in 90 nm due to specific advantages of this technology and great help from foundry • Labs involved: CERN, Strasbourg, Mind Collection electrode Electronics Ioninzing particle Sensitive layer Matrix1 Diode Breakdown test Transistor test A. Marchioro - March '10

  9. Technology evaluation • 2009: • TID evaluation for 90 nm ST and IBM done • 2010: • First temperature characterization of radiation damage annealing at low temperature (-30 deg C) in 130 nm • 65 nm initial evaluation for RH Prerad 10 M 100M TID measurement on ST90 A. Marchioro - March '10

  10. IP Cells • 2009: • General purpose LVDS cells • Low power modified LVDS IO driver/receiver • I2C slave block • “Prompt” radiation detection cell (obligatory for future “exportable” designs) • Bandgap • 2010: • Generic PLL in 130 and 90 nm • E-Link macro • General description • I2C slave port with TMR • 4 or 7 internal addresses available • Din and Dout buses • Deliverables • Verilog • RTL • Gate level • Macro cell: • Abstract • Layout • Timing files • Dimension: 130x130 um2 • Gate count: 1850 A. Marchioro - March '10

  11. The CERN ASIC support website http://cern.ch/asic-support Download Design Kits and access technical documents (restricted access) Information about MPW runs and foundry access services. Communicate news and User support feedback forms and access request forms. A. Marchioro - March '10

  12. Essential support: TRAINING • Workshop sessions • 1st session: 26/10 – 30/10, 2009 (CERN internal engineers, “pilot” run) • 2nd session: 16/11 – 20/11, 2009 (CERN) • 3rd session: 30/11 – 4/12, 2009 (IN2P3, Strasbourg, France) • 4th session: 1/2 – 5/2, 2010 (CERN) • 5th session: 15/2 – 19/2, 2010 (CERN) • 6th session: 1/3 – 5/3, 2010 (CERN) • 7th session: End of April 2010 • Statistics • 10 engineers/session. • 60 engineers in total. • Support • Technical: K. Kloukinas, B.vanKoningsveld • Secretarial: E. Dho A. Marchioro - March '10

  13. Other activities • Negotiations of Contracts with Companies • Foundry • Foundry broker (CERN has most advantageous conditions!) • CAE Tools • Packages acquired through WP1 funds is now distributed for free to HEP Institutes • Export Issues • Negotiation with US Export Authorities, interface to DoE • Harmonization of strategies for insuring easyhandlingof RH chips and systems • Great help from CERN legal office A. Marchioro - March '10

  14. Plans for 2010 and beyond • Continue to support Institutes involved in HEP designs • Extend contract for support of new design methodology support to 90 and 65 nm • Complete RH 90nm library and essential macro blocks (SRAM, special IO, PLL etc.) • 90 nm irradiation test for SEU (dual-well vs. triple-well) • First 65 nm irradiation tests for TID • Restart regular Microelectronics User eXchange (MUX) meetings with tutorial seminars from industry experts A. Marchioro - March '10

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