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Administrative Issues

Administrative Issues . Exam date candidates CW 7 * Feb 14th (Tue): 10-12 * Feb 16th (Thu): 10-12 CW 8 * Feb 24th (Fri): 14-16 CW 9 * Feb 28th (Tue): 14-16 * Feb 29th (Wed): 14-16 (cool date for an exam  ) * March 1st (Thu): 10-12. Multiprocessing Support.

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Administrative Issues

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  1. Administrative Issues • Exam date candidates • CW 7 * Feb 14th (Tue): 10-12 * Feb 16th (Thu): 10-12 • CW 8 * Feb 24th (Fri): 14-16 • CW 9 * Feb 28th (Tue): 14-16 * Feb 29th (Wed): 14-16 (cool date for an exam ) * March 1st (Thu): 10-12

  2. Multiprocessing Support Tannenbaum (3. ed)Chapter 8 • Parallel computer architectures • OS design issues

  3. Parallel computer architectures • Is parallel computing a good idea? • Which parallel computing designs exist?

  4. P1 Input P2 V O/P P3 Parallel Processing Motivation • Single Processor is a Single Point Of Failure (SPOF) • Not tolerable in critical applications (e.g. crash while writing thesis ) • Redundancy helps, e.g. Triple Modular Redundancy (TMR) • Why not just double? • CPUs usually have other detection mechanisms for critical failures…

  5. Parallel Processing Motivation Performance gain through clock rate Power consumption? Implications?

  6. Parallel Processing Overview • Flynn’s Taxonomy • Single instruction single data (SISD) streamno parallel operation • Single instruction multiple data (SIMD) streamvector and array processors, MMX & SSE instructions • Multiple instruction single data (MISD) streamnever implemented • Multiple instruction multiple data (MIMD) streammulticore, multiprocessor

  7. Parallel Processing Overview • Past:Multithreaded Processors • No real parallelism, just increased thread switching • Choose two threads • If one blocks, the other one runs after only • Present:Symmetric Multi-Processors SMPs • Uniform Memory Access (UMA) • Nonuniform Memory Access (NUMA) • Future: Heterogeneous MP • General purpose CPUs • General purpose GPUs • Specific coprocessors • Specific accelerators • Reconfigurable HW

  8. SMPs Message-passingmulticomputer DistributedSystem Shared-memorymultiprocessor

  9. SMPs: Bus-based UMA Caching +private memory No caching Caching Scalability?

  10. SMPs: Crossbar-switched UMA Scalability?

  11. SMPs: Multistage Network UMA Memory addressing scheme Network of 2x2 switches A  X, X  AA  Y, Y  AB  X, X  BB  Y, Y  B

  12. SMPs: Multistage Network UMA 011 sends READ (a) to module 110001 sends READ (b) to module 001 Scalability?n CPUs x n memory units: n/2(log2n) switchesOther problems?

  13. Intel’s Single-Chip Cloud Computer (SCC)

  14. SMPs: Non-Uniform Memory Access (NUMA) • Single address space • Load/Store interface • Access times differ!

  15. Parallel computer architectures • Is parallel computing a good idea? • At least there is no better idea right now... • Clock rate improvement is too expensive(heat dissemination) • Which parallel computing designs exist? • Flynn‘s taxonomy: SISD, SIMD, MISD, MIMD • MIMD: Multithreaded, SMPs, Heterogeneous Multiprocessors • SMPs: UMA, NUMA

  16. Multiprocessor OS Types • Private OS per node • Master/Slave • Shared OS

  17. Private OS per node • Shared HW, CPUs & memory partitioned statically • Soft Resources? Processes, pages, disk…

  18. Master/Slave Central coordinating instance Pros? Cons?

  19. Shared OS • Now every user process can invoke the OS locally • No master CPU bottleneck, yet resource sharing • Other problems?

  20. Multiprocessor OS issues • Synchronization • Switching off interrupts? • TSL? • Covered in the DS part • Scheduling • What to run? • Where to run? • Which combinations? • Covered in the exercise

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