Project Sponsor / Advisor / Mentor: Dr. Daniel Phillips

1. Multidisciplinary Engineering Senior DesignProject 6505: Multi-channel Biomedical Signal Acquisition SystemPreliminary Design Review11/11/2005 Project Sponsor / Advisor / Mentor: Dr. Daniel Phillips Team Members: Jim Massaro, Charles Spuckler, and Matthew Huff Kate Gleason College of Engineering Rochester Institute of Technology

2. Project Overview • Background • Epilepsy • 1% of world population suffers from epilepsy • Less than 50% have a detectable cause • 25% have no means of controlling or predicting seizures reliably • Current Methods of Treatment / Predicting Seizures • Medication • Surgery • Seizure sensing / predicting dogs • Electroencephalogram (EEG) signal analysis

3. Project Overview • Proposal • Create an MCU based embedded data acquisition and processing system that will filter and digitize multiple EEG output channels which will then be sent to a real-time signal processing system. The system output will be compatible for connection to the primary destination of a multiple DSP based processing and analysis system then to a PC or workstation for storage and offline processing and analysis.

4. Project Rationale • Why not just find a DSP with the necessary ADC properties and be done with it? • Minimize DSP requirements and acquisition time • Allows for more time spent in signal processing • Specialized system more efficient at receiving and converting data • Makes a senior design project of converting an analog EEG system into a digital system seem more feasible • Able to be used with continuation for DSP senior design project

5. Initial Steps of Design Process • Met with sponsor to receive more specific information on system requirements, limitations (budget), and expected deliverables • Initial system design was produced with basic functionality derived from requirements list • System specifications were created and proposed for approval of sponsor • Rough time table was created and individual responsibilities within the group were decided

6. System Requirements & Critical Parameters • Sampling rate and digital bit resolution high enough so that data can be considered synchronous and accurate: required to be at least 1 kHz and 12 bits • Able to convert, process and transmit up to 23 analog EEG signals in one sampling period • Signals filtered for any noise encountered between EEG machine and system without modifying original signal • Serial output connection compatible with present Texas Instruments DSP chip available • System calibration command available to user • Error checking capability for data transmitted • System electrically isolated from all peripherals to ensure user and patient safety • Able to apply known input signals and test output for accuracy • Overall price of system not to exceed $1000

7. Initial System Design for Functionality

8. Proposed System Specifications • Variable output bit resolution: 16, 14, 12, 10, and 8 bits over a range of ±6.5V (maximum range of EEG output signals) • Variable sampling rate: 1000, 500, and 200 Hz • 23 analog inputs available (number of outputs on EEG provided by sponsor) • Serial connection acting both as output of system and input for variable settings and system commands with McBSP protocol used to maintain compatibility with TI DSP • Output data format (as determined by McBSP protocol) will include Header, Data, and Error Code • User defined number and order of outputs

9. Proposed System Specifications(cont.) • User controls from DSP to include start converting (including parameter setup), stop converting, and calibrate • Anti-aliasing filters matched to each sampling frequency: cutoff frequencies of 35, 70, and 120 Hz for sampling rates of 200, 500, and 1000 Hz respectively and maximum attenuation at 100 dB for Nyquist rate • Internal calibration signal source as available input to system • Required power input of 120 Vac (standard grounded plug) • Power supply electrically isolated from peripherals of system at level to meet biomedical application requirements • LED indicators for Power and System Error

10. Rough Gantt Chart for Project Timeline: Fall Quarter

11. Individual Responsibilities / General Work Distribution Outline • Jim • EEG signals and machine information • Filter design specification • Charles • Filter Design implementation • Design layout, PCB integration, PSPICE simulation • Matt • Microcontroller information • McBSP protocol information

12. EEG Specifications • Signal Conditioning • Two input signals with differential amplification CMRR > 10,000 • High-pass filter adjustable cut-off frequencies 0.1 Hz, 0.5 Hz, 1 Hz, and 5 Hz • Low-pass filter adjustable cut-off frequencies 15 Hz, 35 Hz, 70 Hz, and 120 Hz • Notch filter for 50/60 Hz • Amplification of 50 μV signals with total gain 20,000 V/V • Signal Types • Cerebral EEG frequency range >0 to 70 Hz • ECG frequency range >0 to 100 Hz

13. Block Diagram of EEG Signal Processing

14. EEG Signal Reconstruction • Objective • To successfully digitize the EEG signals without degradation • Anti-Aliasing filter frequency response must match the frequency response of the EEG • Solution • Build three filters • Sampling rate of 1000 Hz cut-off 120 Hz • Sampling rate 500 Hz cut-off 70 Hz • Sampling rate 200 Hz cut-off 35 Hz

15. System Design Process and Description Detailed part descriptions and reasons for selection

16. Design Process • Sampling • Synchronous sampling • Needed sample and hold and filtering systems to each input • Sponsor confirmed that a small time delay between signals would be acceptable • Only one sample and hold is needed • Anti-aliasing filter • Different sampling time would require different filters to avoid aliasing • Adjustable anti-aliasing filter was suggested • A large number capacitors of would need to be changed • Switched capacitor filter did not meet specifications

17. Design Process • Microcontroller • Communication Capability in Hardware • RS-232 or USB protocol • USB 2.0 would be preferable for higher transfer rates – 1.5 Mbytes/sec • SPI to be used with McBSP protocol • Calibration Signal • Needed as selectable analog input to system • Single 5 VDC source from power supply

18. Final Design

19. Multiplexers • Two input or sampling multiplexers • Receives inputs from the EEG • MCU controls sampling • Switching time less than 150 ns and input range of +/-6.5 volts • One 4 input multiplexer • Filter selection • Switching time less than 150 ns and output range of +/-6.5 volts

20. Anti-Aliasing Filter • Three filters designed for different sampling frequencies • Cut-off frequency of the filters made to match filters of the EEG • 35 Hz for 200 Hz sampling frequency • 70 Hz for 500 Hz sampling frequency • 120 Hz for 1000 Hz sampling frequency • Feature large attenuation of 100 dB at half the sampling rate to prevent aliasing • Signal from sampling MUX into filters • Output into filter MUX to ADC

21. Microcontroller • PIC18F4550 was chosen • Capable of controlling the different parts of the system • 48 MHz clock speed fast enough to take samples and prepare the data to send to the DSP within the shortest sampling period. • Also has a USB connection which will help with interacting with the system. • 34 I/O for controlling the system, reception of ADC data, and serial output • Control lines to the multiplexers, and ADC. 2 kbytes of RAM to hold up to 23, 16 bit signals, error codes, and headers

22. Microcontroller Communication • Microcontroller will be able to receive commands from the DSP • Commands include start conversion, stop conversion, calibrate. • It will also receive setup commands and information • Includes sampling frequency, bit resolution, and which lines to sample in which order. • Communication will happen through McBSP • McBSP is supported by the DSP and is capable of sending data at the needed speeds. • Will also prepare the converted data to be sent to the DSP • Preparation includes adding a header and error checking codes • Controls when the sampling occurs, input order, and bit resolution

23. Analog to Digital Converter • ADS7805 was chosen • Features a fast sampling period of 10µs • Allows the microcontroller enough time to process the data and allows for a short delay between sampling of all input signals • 16 bit resolution • Available reference input to set ADC voltage range to match the range of the EEG output signals • Sample and hold circuit included • Receives its input from the filter MUX and sends data to the microcontroller • Conversion controlled by microcontroller

24. Power Supply • NFS40-7908 • Medical power supply capable of outputting the voltage levels needed by the other components • Power output greater than the amount consumed by the other components • Isolated to help protect a person connected to the EEG machine and the system itself. • Supplies +12, -12, and +5 voltage to all components

25. Detailed Design

26. Plans for Test and Implementation Senior Design II Outlook

27. Test Plans and Integration • Test Plans • Verification of design • Each component tested individually • No unexpected outputs occur between components • Timing and response of each component to ensure an accurate sampling rate • Integration • System construction on a PCB • PCB software available on PSPICE • Experience must be gained with software

28. Rough Timing Diagram

29. Testing Input Multiplexer and Filters • Input Multiplexer testing • Simulation using PSPICE • Hardware tested using oscilloscope • Compared and documented • Filter Testing • Filter simulated in PSPICE • Input frequency can be varied • Hardware tested using a breadboard and a signal generator • Filter timing has to be determined

30. ADC and MCU Testing • MCU Testing • MCU software designed in PICDEM Full Speed USB demo kit • DSP provided to test communication link • Output viewable through DSP software • Experience must be gained with the software • MCU with ADC testing • ADC critical component • The hardware tested with controlled input

31. EEG Compatibility • Objective • All components tested individually • Assemble the system into analog and digital portions • Main concern is that the acquisition system doesn’t degrade the output of the EEG • Solution • EEG is capable of taking DC inputs and processing through external outputs • Electrode signals simulated by controlled input • Output of each filter to match the output from the EEG

32. Block Diagram for testing with EEG

33. Bill of Materials

34. Work Distribution/Responsibilities for Senior Design II • Charles Spuckler • Simulation of filters • Gain experience with PCB software and integration • Hardware Design and test of filters • System integration testing with EEG • Jim Massaro • Gain experience with DSP software • System integration testing with EEG • Hardware Design and test of filters • Matthew Huff • ADC and MCU software design and integration • Testing MCU with sampling MUX • System integration testing with EEG

35. Senior Design II Gantt Chart

36. Questions? Suggestions?

37. Filter for 200 Hz Sampling

38. Frequency Response of the Filter

39. McBSP and SPI Compatability When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or a slave. The McBSP is a master when it generates clocks. When the McBSP is the SPI master, CLKX drives both its own internal receive clock (CLKR) and the serial clock (SCK) of the SPI slave. The FSR and CLKR signals should not be used in SPI mode. These do not function as SPI signals like the FSX and CLKX signals. In conjunction with CLKSTP enabled, CLKXM = 1 (in PCR) indicates that the McBSP is a master, and CLKXM = 0 indicates that the McBSP is an SPI slave. The slave enable signal (FSX/SS) enables the serial data input and output driver on the slave device (the device not providing the output clock).