VLSI Systems Design

1. VLSI Systems Design EE116B (Winter 2001): Lecture #1

2. Course Goals • Main objective • overview of various steps in digital CMOS VLSI design • circuit, logic, and architecture issues • design tools and techniques • engineering issues for performance, noise, testability etc. • Approach • lectures to present VLSI design concepts • regular homework will test you on the concepts • design assignments will expose you to CAD tool based VLSI design

3. You will NOT learn... • Device physics • Semiconductor processing • Fancy circuits • Advanced logic • Computer architecture • Writing CAD tools • Analog VLSI • VLSI using technologies other than CMOS (e.g. bipolar, GaAs etc.)

4. Schedule • Lectures • TuTh 10-11:50AM @ Boelter 5440 • Discussions (supervised by TAs) • Section 1: Fr 12-12:50PM @ Boelter 5252 • Section 2: Th 12-12:50PM @ MS 3915A • Laboratory Sessions (supervised by TAs) • Section 1: We 12-3:50PM @ EIV 44-110 • Section 2: Tu 12-3:50PM @ EIV 44-110

5. More on Lab Sessions • There will not be any formal “lecturing” in the labs • The purpose is to have a period of time when • you’ve guaranteed access to computers for design assignments • SEASnet labs are very crowded • TA is present to supervise & help you with the design assignment • I can come and see everybody’s progress and explain things • Usually, I will come for an hour at the beginning of every lab • However, the four hour lab sessions are not at all enough… • be prepared for spending LOTs of time on design assignments outside the regular lab sessions (44-110 EIV is closed) • Coming to lab sessions is stronglyencouraged • otherwise you will miss important assignment related announcements and fall behind very easily • Ultimately, you are responsible for timely submission

6. Course Staff • Instructor: Mani Srivastava • Email: mbs@ee.ucla.edu • Tel: 310-267-2098 • Office: 7702-B Boelter Hall • Office Hours: Tu 4-5, Th 1-2 • Lab Office Hours: Tu 12-1, We 12-1 • Administrative Assistant: Leticia Marr (Letty) • Email: letty@ea.ucla.edu • Tel: 310-267-1954 • Office: 7440-D Boelter Hall • Hours: M-F 8-5

7. Course Staff (contd.) • Teaching Assistant #1: Pavan Kumar • Email: pavkumar@ee.ucla.edu • Tel: (310) 206-8785 • Office: 5th Floor Graduate Student Area • Office Hours: TBA • Teaching Assistant #2: NONE ASSIGNED YET • Email: ??? • Tel: ??? • Office: ??? • Office Hours: ???

8. The TA Situation (as of Jan 3) • The EE Dept. has not assigned the two Teaching Assistants needed to staff all the discussion & lab sessions • it seems we will have only one TA • Impact: no discussion sections • Please use my office hours (or schedule appointments with me) • Seek help during lectures

9. Prerequisites & Grading • Prerequisites • understanding of circuits and digital logic & systems • EE115c, EE16, some advanced digital design course (any of EE116L, EE116C, EE116D etc.) • Grading Final: 30% Midterm (1) + Surprise Quizzes: 20% Homework (2-3) 15% Lab assignment (2-4) 35% Regular attendance is mandatory. Unsatisfactory attendance and participation in the class (lecture, lab, discussion section) will reduce your final score by up to 20%.

10. Cheating & Plagiarism • My apologies if you are one of the vast majority of students who don’t resort to academic dishonesty • but unfortunate incident last year due to some bad apples • What is cheating & plagiarism? • Acting dishonestly, practicing fraud • Stealing or using other people’s writings or ideas • E.g. from other students, other sources such as web sites, solutions from previous offerings of this course etc. • Note that it doesn’t have to be literal copying – stealing ideas but presenting in a different style is still cheating and plagiarism. • You are also guilty if you aid in cheating & plagiarism • My policy: zero tolerance • HWs & design assignments: zero points on the assignment • Exams & quizzes: “F” grade for the course, report to Dean • More than 1 incident: : “F” grade for the course, report to Dean

11. Books • Essential • Digital Integrated Circuits : A Design Perspective; Rabaey, Jan M . Prentice Hall PTR .; 11/1995; Hardcover; $89.00; • The Designer's Guide To VHDL; Ashenden, Peter J . / Ashenden. Morgan Kaufmann Publishing; 10/1995; Softcover; $56.00; • Helpful • Principles of CMOS VLSI Design : A Systems Perspective; Weste, Neil H. E. / Eshragian, Kamran. Addison Wesley; 04/1993; Hardcover; $54.95; • On-line book: http://vlsi.wpi.edu/webcourse/toc.html

12. Lecture Notes • Lecture slides are your primary reference material • material from places other than the textbook • I will hand out copies of lecture slides • 3 or 6 slides to a page • Powerpoint and pdf files on the web site if you want higher resolution copies of the slides • Note that the slides are organized by topic • typically, each “Lecture” will span several classes

13. Computer Accounts • You need a SEASnet account (your personal account) • SEASnet will allocate you 100MB disk space for this course • If you don’t have one, get one immediately • SEAS students: http://www.seas.ucla.edu/acctapp • Non-SEAS students: SEASnet office 2567 Boelter • This class requires CAD tools that are available only on sunugrad.seas.ucla.edu, and function only under X11 • you need to remotely login to sunugrad.seas.ucla.edu from a computer that has X11 server • E.g. from home/dormitory: • FAST connection (DSL, cable modem, ethernet) • Linux or equivalent with X11 environmentor, Windows PC with X11 server software (e.g. eXceed)

14. Course on the Internet • Course home page: lectures, handouts etc. • http://www.ee.ucla.edu/~mbs/courses/ee116b/2001w • To save trees, I will handout lecture notes with 6 slides per page • You can visit the web site for cleared copies of the notes • Course mailing list • ee116b@desp.ee.ucla.edu • I will use this for class announcements • you can use it to mail to the class for queries relevant to the course • you need to subscribe by doing the following: • go to http://desp.ee.ucla.edu/mailman/listinfo/ee116b-2001w and subscribe to the mailing list ee116b-2001w • follow the instructions in the email that you’d receive • Remember to subscribe to the mailing list – it is your responsibility • otherwise you may miss important announcements

15. Groups for Design Assignments • The design assignments are to be done in groups of 2 or 3 • same team for ALL design assignments • assignments will be partially “scaled” to group size • your partner(s) must be from the same lab session as you • in the past, some students have even chosen to do the lab assignments alone – though not advisable, it is your choice • Please form your group prior to your first lab session • i.e. TODAY for those of you enrolled in the Tuesday lab • Send me email if you are unable to find a partner • if somebody remains unassigned, I will randomly break some groups of 3 • You will be given a “group number” which you should write on all your design assignment submissions

16. Final Words • This is a difficult and demanding course • lots of time needed for design assignments • But, I hope that you will find it to be practical and useful for your careers • Advise: focus on learning and doing your best, and not on the grades • hard work always pays off

17. Questions?

18. Issues & Trends in VLSI Design • Exponential growth in integration complexity • lots of transistors! • Advances in semiconductor technology • not just digital & analog - RF, optical, MEMS • Relentless digitization of things around us • computers getting embedded everywhere • New user requirements • portable, wireless, low-power

19. The First Computer [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

20. ENIAC - the First Electronic Computer (1946) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

21. Today’s Computers

22. Moore’s Law • By Gordon Moore, Intel’s co-founder # of transistors on a diedoubles every 1 to 2 years • From 1958 to 1994 • F (feature size) : 1/50 • D2 (die area): x170 • PE (packing efficiency - # of transistors per minimum feature area): x100 • N = D2xPE/F2 = 50E6! • No sign of slowing down! • “SoC” or System-on-chip

23. Evolution in Transistor Count

24. Evolution in Complexity [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

25. Evolution in Speed & Performance [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

26. Sony Playstation II • 128-bit CPU “Emotion Engine” • 0.18 micron process • 300MHz, 6.2 GFLOPS, 3.2 Gbytes/second • 10 floating point multiply-accumulators and 4 floating point dividers • 3x floating point performance of 500 MHz PIII • Graphic synthesizer cgip • 0.25 micron chip • 42.7M transistors • 16.8x16.8 mm^2 die • 2560-bit datapath • 48 Gbytes/sec memory bandwidth • 75M polygons/sec, 2.4 Gpixels/sec

27. Silicon in 2010 Die Area:2.5x2.5 cm Voltage:0.6 V Technology:0.07 m [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

28. The Design Problem Source: sematech97 A growing gap between design complexity and design productivity [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

29. Profound Impact on the way VLSI is Designed • The old way: manual transistor twiddling • expert “layout designers” • entire chip hand-crafted • okay for small chips… but cannot design billion transistor chips in this fashion • The new way: using CAD tools at high level • tools do the grunge work… • high levels of abstractions • synthesis from a description of the behavior • libraries of reusable cores, modules, and cells Chip design increasingly like object-oriented software design!

30. Design Abstraction Levels [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

31. The Transistor Twiddling & Rectangle Pushing Approach

32. Design with CAD Tools

33. Can’t Ignore “Transistor Twiddling” • Worthwhile when design is to be used over and over again • module libraries • parts of commodity parts (memories, processors) • Performance limits to abstraction and CAD tools • global effects: clock, supply • interconnects • deep-submicron • power, debugging • analog

34. The Old and the New Intel 4004 Microprocessor Intel Pentium Microprocessor [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

35. Pentium III • Statistics • 28.1M transistors • 0.18 micron, 6-layer metal CMOS • 106 mm^2 die size • 3-way superscalar, 256K L2 cache, 133 MHz I/O bus

36. Core-based Design: System on Chip • SC3001 DIRAC chip (a radio receiver) from Sirius Communications

37. Topics Covered in this Course • Review of CMOS circuits (EE115C) • MOS transistor, switch model, gates etc. • CMOS processing technology • how are chips fabricated? • layout rules • Structured VLSI design & layout (Rabaey CH 11) • cells, cell libraries, routing, layout styles, higher level design flow • Design using hardware description languages • VHDL Language • modeling, synthesis in VHDL

38. Topics Covered in this Course (contd.) • Chip architecture concepts (Rabaey CH 7) • Arithmetic subsystems • Datapath and control • Design for Testability (Rabaey CH 11) • testing chips for defects, types of defects, designing chips so that detecting defects is easier • Low power design (Rabaey CH 4 & 7) • designing for low power, voltage scaling, exploiting architecture tricks for low power • Parasitic & interconnect (Rabaey CH 8) • R, C, and L parasitics, packaging • Performance issues