Design and Implementation of VLSI Systems (EN0160)

1. Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill, Weste/Addison Wesley]

2. Last time: Lecture 03: CMOS fabrications • How do transistors make up different CMOS gates? • Today: • Fabrication of CMOS gates

3. What needs to be fabricated?

4. Top view

5. Fabrication Target: Inverter GND VDD

6. Gate layouts is decomposed into primitives layouts that would be printed in sequence

7. Wafer preparation

8. UV light Reticle field size 20 mm × 15mm, 4 die per field 5:1 reduction lens Image exposure on wafer 1/5 of reticle field 4 mm × 3 mm, 4 die per exposure Serpentine stepping pattern Wafer Photolithography is used to print desired patterns on the wafer masks The feature size directly depends on the wavelength of your lithographic system

9. P Type start wafer

10. Grow P-epitaxial layer

11. Spin Resist Coating

12. Expose N Well Mask

13. Develop resist (remove resist exposed to light)

14. Implant N Well

15. Remove Resist

16. (possible pre-spin action, e.g., deposit) Spin resist Expose (using mask) Develop resist ACTION (e.g., implant, etch, oxidize) Remove Resist Main 5-6 Steps: SEDAR

17. Anneal wafer to grow new oxide layer and diffuses N well

18. Remove oxide from anneal

19. Spin Resist

20. Develop resist

21. Expose resist with active diffusion mask

22. Grow oxide on exposed surface

23. Remove resist

24. Grown thin oxide over silicon surfaces

25. Deposit poly using Chemical Vapor Deposition (CVD)

26. Spin resist – expose resist using the GATE mask – develop resist – etch poly

27. Remove thin oxide layer where exposed

28. Spin resist – expose with P implant mask – develop resist – implant P

29. Spin resist – expose with N implant mask – develop resist – implant N

30. Remove resist – anneal wafer – oxide etch

31. Deposit oxide using CVD – spin resist – expose Contact mask – develop resist - etch contact hole – remove resist

32. Deposit metal 1 – spin resist - expose metal 1 mask – develop resist - etch metal – remove resist

33. UV light Mask oxygen exposed photoresist photoresist Silicon dioxide oxide Silicon substrate Exposed Photoresist Photoresist Develop Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment and Exposure RF Power RF Power RF Power RF Power Dopant gas Ionized CCl4 gas Ionized oxygen gas Ionized CF4 gas Silane gas oxygen photoresist oxide oxide poly gate oxide polysilicon top nitride drain G G S D G D S D S Polysilicon Mask and Etch Oxide Etch Oxidation (Gate oxide) Polysilicon Deposition Photoresist Remove gate oxide Scanning ion beam Contact holes Metal contacts silicon nitride resist Active Regions G G ox D S S D Ion Implantation Metal Deposition and Etch Nitride Deposition Contact Etch Fabrication Summary

34. Spin polyimide – spin resist – expose via 1 mask – etch via – remove resist

35. Deposit metal 2 – spin resist – expose metal 2 – etch metal – remove resist

36. Spin polymide – spin resist – expose via 2 mask – etch via – remove resist

37. Deposit metal 3 – spin resist – expose metal 3 mask – develop resist – etch metal – remove resist

38. Spin polyimide – spin resist – expose passivation mask – develop resist - etch poly – remove resist – deposit nitride – spin resist – expose passivation mask – etch nitride – remove resist

39. More metal layers?

40. Excimer laser (193 nm ArF ) Illuminator optics Reticle library (SMIF pod interface) Beam line Wafer transport system Operator console Reticle stage Wafer stage Auto-alignment system 4:1 Reduction lens NA = 0.45 to  0.6 The printer

41. Today: Reviewed fabrication process Next time: How to print different gates? Summary