COTS for on-detector timing distribution. Status report and preliminary tests.

1. COTS for on-detector timing distribution. Status report and preliminary tests. A. Aloisio, R. Giordano University of Naples ‘Federico II’ and INFN aloisio@na.infn.it rgiordano@na.infn.it

2. Overview • SerDes in the ETD framework • COTS for the FCTS • Testing the NSC DS92LV18 • Info from the foundry: layout, process, … • Preparing for the rad tests • Work in progress • Conclusions SuperB Workshop - SLAC, Oct.09

3. Setting the scene FCTS: Fast Control and Trigger System FE: Front End ROM: Read Out Module • In the ETD framework, serial links with different features have been specified • FCTS-to-FEE distributes timing on detector: it needs fixed latency, low jitter, rad tolerance From : D. Breton & U. Marconi Proposal for the Electronics Trigger and DAQ architecture of SuperB June 8th 2009, Perugia Workshop SuperB Workshop - SLAC, Oct.09

4. Why COTS ? • SerDes embedded in SRAM FPGAs very likely can not be used • Off-the-shelf components could be selected and qualified for rad-tolerance • Glue-logic could go in anti-fuse FPGAs • Alternatives: custom design, SLHC GBT project, …

5. The NSC DS92LV18 SerDes • Full duplex transceiver • 18bit payload, 20bit symbol, 15 to 66 MHz • Up to 1.3 Gbit/s • LVDS serial I/O • 3.3V, ~1 W (max) SuperB Workshop - SLAC, Oct.09

6. DS92LV18 Plus/Minus • Plus • Simple protocol -> fixed latency • 20bit simbol, compatible with FPGA embedded transceivers • Tolerant TX vs. RX clock frequency scheme • 0.25 um CMOS process already qualified (not the part) • Cheap (<10€) • Minus • 1 Gbit/s range • Encoding required externally

7. Coax cables RX TX 18 18 TX clock RX refclk RX clock Evaluation Board • Eval board available from National • 2 transceivers + 1 dual-transmitter • LVDS serial streams on SMA connectors • Data/controls/clocks on test points SuperB Workshop - SLAC, Oct.09

8. Latency test • Fixed latency, after loss-of-lock, reset, power cycle • Tlat = 72ns @ 61.2 MHz (5ns coax cables) TX clock Tx-D0 Rx-D0 RX clock (recovered) SuperB Workshop - SLAC, Oct.09

9. Physical protocol start stop start stop start • 20bit symbol: start, 18bit payload, stop • Guaranteed transitions at the symbol boundary • No encoding provided, pattern is transmitted as-it-is • 61.2 MHz x 20 -> 1.2 Gbit/s, 1.1 Gbit/s user bandwidth,1 UI = 817 ps SuperB Workshop - SLAC, Oct.09

10. Errored Stream stop start Missing start • Errored streams with missing start/stop are emulated by a data generator • Errors (1 every 200 symbols) are injected into the deserializer to study loss-of-lock and error recovery timing • ‘Training’ or ‘Sync’ pattern are needed to achieve a new lock RX Error flag RX refclk SuperB Workshop - SLAC, Oct.09

11. SYNC patterns Modified SYNC Pattern • A SYNC pattern is a fixed payload of 9bit high followed by 9bit low: it is an unambiguous pattern to align with • It is generated on-demand by the TX to favour the lock: specific user payloads may disrupt the process • We have used a modified pattern to stress the CDR 18 UI 18 UI payload payload SYNC Pattern 9 UI start 9 UI start start payload stop stop

12. Loss-of-lock Error injection Error flag • Each and every missing start/stop triggers a loss-of-lock • Then, the RX automatically tries to lock on the stream • Lock is (should be) guaranteed by SYNC patterns: BELLE reports a few problems with older components, no issues have been seen during our tests RX recovered clock LOCK* Loss-of-Lock Lock achieved SuperB Workshop - SLAC, Oct.09

13. Recovery time Error injection • Recovery time with modified SYNC pattern is 55 clock cycles • In our setup, RX refclk is derived from TX clock (too optimistic !) • 500 to 1000 clock cycles can be expected in a real working condition (see datasheet) • Lock is guaranteed Error flag RX recovered clock LOCK* 890 ns 250 ns LOCK* Histogram SuperB Workshop - SLAC, Oct.09

14. Error close-up Error injection • Latency of up to 5 clock cycles between error and loss-of-lock, data corrupted immediately • Duty cycle distortion on recovered clock, then stuck-at-one Error flag RX recovered clock Up to 5 clock cycles LOCK* SuperB Workshop - SLAC, Oct.09

15. Process info • CMOS8 process, 250nm • same as DS92LV1023, qualified by ATLAS, CMS • No SEU/SEL performed up to now on DS92LV18 (National, ESA, CERN, …) • TID test passed up to 100 kRad (National) SuperB Workshop - SLAC, Oct.09

16. from National Semi • TID • SEL • SEFI SuperB Workshop - SLAC, Oct.09

17. DS92LV18 layout Chip layout 5.5 mm 5.5 mm courtesy of National Semiconductor 60 KeV Xray picture serializer deserializer SuperB Workshop - SLAC, Oct.09

18. LNS facility • SEE/SEU tests are planned in 2010 at LNS (Catania, Italy) • 62 MeV proton beam • Heavy ion beams available for LET threshold measurements, if needed • Waiting for Beam Time Unit call & allocation (end 2009) SuperB Workshop - SLAC, Oct.09

19. Work in progress • DS92LV18 • Recovered clock jitter analysis • Payload encoding scheme • FPGA protocol emulation for hybrid links • Rad Tests SuperB Workshop - SLAC, Oct.09

20. Conclusions • DS92LV18 is a candidate for on-detector FCTS implementation • It shows fixed latency and it could also be considered for FEE-to-ROM links, depending upon the total bandwidth required • Encoding/scrambling to be done externally for DC balance, possibly Error Detection/Correction in the payload • Process already validated by ATLAS, CMS , not the part. • Rad test at LNS in 2010, with 62 MeV proton beam SuperB Workshop - SLAC, Oct.09

21. Acknowledgement • We wish to thank Kirby Kruckmeyer, Radiation Effects Engineering Manager, Hi-Rel Operations (National Semiconductor) for his suggestions and precious support • We are also grateful to Giacomo Cuttone and his team at LNS for the support in preparing the rad test setup; to Paolo Russo and Giovanni Mettivier (Univ. of Naples and INFN) for the Xray analysis of the DS92LV18