1 / 31

CCS Hardware Test and Commissioning Plan

CCS Hardware Test and Commissioning Plan. ECAL Off-Detector Electronics Workshop 7-8 April. 2005 Kostas Kloukinas CERN. Overview. CCS Development Status Production Plan CCS during Integration and Commissioning. The FEC-CCS System. Design satisfy the requirements from: Tracker ECAL

zia
Download Presentation

CCS Hardware Test and Commissioning Plan

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CCS Hardware Test and Commissioning Plan ECAL Off-Detector Electronics Workshop 7-8 April. 2005 Kostas Kloukinas CERN

  2. Overview • CCS Development Status • Production Plan • CCS during Integration and Commissioning Kloukinas Kostas

  3. The FEC-CCS System • Design satisfy the requirements from: • Tracker • ECAL • Preshower • Pixel • RPC • Three components: • mFEC: small mezzanine card suitable for VME and PCI utilization. • PCI-carrier: motherboard for one mFEC • FEC-CCS: VME motherboard for 8 mFECs. FECtracker = CCSecal* Kloukinas Kostas

  4. mFEC & PCI carrier • mFEC on a PCI carrier board • to facilitate development work • to be used in the lab and test beams. Kloukinas Kostas

  5. FEC-CCS V2 (Prototype) VME Interface FPGA mFECs VME backplane ECAL backplane TTC input Trigger FPGA Kloukinas Kostas

  6. FEC-CCS V3 (Final) • V2 to V3 modifications: • Splitting of 1-wire bus for temperature sensors and serial ID chip. • Reassignment of JTAG backplane signals. • QPLL & TTCrx control lines. • Routing of spare FPGA lines at the P2 connector. • One board assembled. • Tested O.K. Kloukinas Kostas

  7. Prototype Test Status • VME to Local Bus interface is O.K.. • All 8 mFECs can be and accessed from the VME bus. • Conforms to the VME 64x “plug & play” standard. • VME Interrupter is tested. • Various Functions • Electronic Serial Number tagging using a serial ID chip. • Airflow temperature monitoring of the OPTOBAHNs on mFECs • Fast Timing path is tested. • TTCrx – Trigger FPGA – mFECs – control rings. • Send trigger commands to FE and DCC. • Power consumption (measured) • Card fully equipped with 8 mFECs • 7A @ 3.3V, 1A @ 5.0V => ~30W dissipated • Pending Issues: • TTS signal functionality. • DCC-CCS-TCCs integration tests. • VME bus JTAG basckplane controller access. Kloukinas Kostas

  8. Pre-Production Status • FEC-CCS: • Version 1: First prototype. • 2 units have been fabricated. • Were used in the TRACKER test beam and in the ECAL test-beam setups (summer 2004). • Version 2: Second prototype. • 8 units have been fabricated. • All units are tested and fully equipped with mFECs. • They are available for distribution. • Version 3: Final version. • Pre-production of 10 boards is in progress. • 1 unit delivered (11/3) and currently being tested • 9 more will be delivered around early April. Kloukinas Kostas

  9. FEC-CCS Test Bench • XDAQ (HAL) framework • Full plug&play support • Software development by: • E. Vlassov • F. Drouhin CERN scientific Linux >_ Kloukinas Kostas

  10. Component Traceability • Managing the distributionof FEC-CCS boards. • FEC-CCS Project Website: • proj-fec-ccs.web.cern.ch/proj-FEC-CCS Kloukinas Kostas

  11. Final Production • Tracker: 352 control rings => 44 FEC-CCS boards • ECAL: 368 control rings => 46 FEC-CCS boards • Preshower: 48 control rings => 20 FEC-CCS boards • Pixels: 120 control rings => 16 FEC-CCS boards • RPCs: 25 control rings => 4 FEC-CCS boards ----------------------- 130 FEC-CCS boards • 116 FEC-CCS boards => 930 mFECs • 50 PCI FEC boards => 50 mFECs ---------------- 980 mFECs • Spares should be added…. Kloukinas Kostas

  12. Production Schedule • Production of 900 mFECs is in progress. • Production of 140 FEC-CCS boards to start soon. • All components have been procured • PCB manufacturing and assembly companies found. • Production Testing • Will be done at CERN • Test bench and test procedures are currently under development. Kloukinas Kostas

  13. Integration & Commissioning • FEC-CCS board should facilitate: • Front-End system testing & debugging. • Possibility to run DCC-CCS-TCC(s) standalone. • Enable data taking when LTC-TTCci system is unavailable. Kloukinas Kostas

  14. DCC DCC DCC DCC TCC TCC TCC TCC FMM FMM Controller Final System TTC/TTS signal paths TTCmi Global Trigger Controller TTC Local Triggers TTS TTC ex TTC ex TTC ex TTC ci TTC ci TTC ci TTC ci TTC ci TTC ci TTC ci TTC ci Controller LTC TTS CCS CCS CCS CCS Controller TTC Kloukinas Kostas

  15. FEC-CCS during Integration • When final System is not yet available / operational • Requirements: • Enable Slow Control for the FE electronics. • Generation of Local Trigger Commands and their distribution to the FE and to the OD electronics. • Off-Detector electronics (DCC, TCCs) synchronization at the level of one supermodule. • Implementation: • Hardware • Interface with external signals to synchronize internal operations. • Firmware • Trigger FPGA functionality to allow the generation and distribution of the Local Trigger Commands. • Software • To support these functionalities. Kloukinas Kostas

  16. mFEC mFEC mFEC mFEC mFEC mFEC mFEC mFEC External I/O FEC-CCS Block Diagram • Support for 1~8 control rings per board. • VME 9U board. • VME64x compatible. • Control information passes through the VME bus. • Fast Timing Signals passes through the TTC link. VMEinterfaceFPGA Local Bus VMEbus JTAG Fast Timing signals TriggerFPGA QPLL TTCrx TTC link ECAL TTC/TTS bus Kloukinas Kostas

  17. FEC-CCS Piggy Back Board • ECAL Test Beam Summer 2004 Trigger FPGA logic. • Prepared by Mark Dejardin Kloukinas Kostas

  18. LVTTL to NIM VME RJ2 connector NIM to LVTTL FEC-CCS Multi I/O board • As a replacement of the Piggy Back I/O board. • Propose to build a 3U Rear VME Backplane Transition Board • Connects on spare Trigger FPGA lines. • Only FEC-CCS V3supports this card. NIM I/O 4 IN 4 OUT 1 clock in 1 clock out (+ 4 IN/OUT spares) LVTTL I/O Kloukinas Kostas

  19. Trigger FPGA firmware design CCSLocal Bus Trigger FPGA Piggy Back Board Trigger CommandManager Local Businterface&Control Registers 4 NIM to TTLTTL to NIM translators IN Clk40_L1to mFECs 4 OUT CCS Clock Clk40_L1 TTCrx L1ACCEPT L1 Token Ring Clock Encoder BRCST<7:2> 110 101 111 TTCRX_RDY Clk40 Clk80 QPLL 40MHz TTC Encoder TTC in L1 80MHz B<7:0> 160MHz Clk40 Clk40 Clk160 TTC signalto DCC/TCCs Kloukinas Kostas

  20. Trigger Command Manager (1/4) • FEC-CCS modes of operation • REMOTE: • Trigger Commands as received from the TTCrx chip are being distributed to Token Rings and the ECAL backplane. • Used for Normal Data Taking operation. • LOCAL: • Allow the generation of Local Trigger commands. • Used for system debugging. • Mode Selection • Auto • Remote/Local selection is automating depending on the status of the TTCRX_RDY signal. • Forced LOCAL • User selection Kloukinas Kostas

  21. Trigger Command Manager (2/4) • Mapping of TTC B channel commands to Token Ring Trigger Commands • Trigger Command Assignments on the Token Rings are not common between subsystems. • The FE ASICs decode these commands in a fixed manner. • Mapping of TTC B channel commands to Token Ring Trigger Commands can be done by a LUT in the Trigger FPGA. Kloukinas Kostas

  22. External signals Internal signals External signals LOC_L1 command channel Trigger Command Manager (3/4) • Generation of Local Trigger commands • Local L1 Trigger Command. Kloukinas Kostas

  23. Trigger Command Manager (4/4) Kloukinas Kostas

  24. Wrap Up • Flexible and configurable logic allows for: • Single shot commands. • Single shot Bursts of commands. • Sequence of multiple commands. • Periodic Sequence of multiple commands. • Synchronization with external signals. • Generic design • The Integration Physicist/Engineers can modify the Trigger Generation logic as required for their setup. • Other sub systems could possibly utilize these functionalities • Easy firmware maintenance. Unique version for all subsystems. • Comments & Discussion….. Kloukinas Kostas

  25. Backup Slides Kloukinas Kostas

  26. Piggy-Back PCB • R. Benetta, M. Dejardin Kloukinas Kostas

  27. FEC-CCS Piggy Back I/O board • Prepared for the ECAL Test Beam in Summer 2004. • by Mark Dejardin Kloukinas Kostas

  28. Trigger FPGA Registers Available only for the ECAL Test Beam summer 2004 Kloukinas Kostas

  29. Trigger FPGA design CCSLocal Bus Trigger FPGA Piggy Back Board ECAL Local TriggerManagement Logic Local Businterface&Control Registers BOB NIM to TTLTTL to NIM translators Clk40_L1to mFECs EOB Laser In TDC Start TDC Stop Clk40_L1 Clk40 Laser Out Trigger Insertion Logic Loc L1 CCS Clock Clk40 Clk40 Clk40_L1 QPLL TTCrx 40MHz Clock Management Logic 160MHz TTC signalto DCC Kloukinas Kostas

  30. Overview of CCS Board Kloukinas Kostas

  31. FEC-CCS Production Testing • Production Testing will be done at CERN • Separate Test Benches: • For the mFECs will be PC based. Using PCI carrier boards. • For the FEC-CCS boards will be VME based. • Hardware needed: • PCI bus, preferably allowing hot plug-in. • TTC/TTS backplane driver board. • TTCvi or TTCci . • Software needed • PC software for mFEC testing • Linux software for FEC-CCS testing. Kloukinas Kostas

More Related