Interconnect Working Group

1. Interconnect Working Group 2008 Edition Draft 3 - 4 April 2008 Petersberg, Germany Attendees Shuhei Amakawa, Sitaram Arkalgud,Hans-Joachim Barth, Christopher Case, Harold Hosack, Mauro Kobrinsky, Didier Louis, Larry Smith, Detlef Weber.

2. Robert Geffken Hans-Joachim Barth Alexis Farcy Harold Hosack Paul Feeney Ken Monnig Rick Reidy Mauro Kobrinsky Hideki Shibata Kazuyoshi Ueno Michele Stucchi Susan Vitkavage Eiichi Nishimura Mandeep Bamal Quingyuan Han Robin Cheung Didier Louis Katsuhiko Tokushige Masayoshi Imai Greg Smith Detlef Weber Anderson Liu Scott Pozder Osamu Yamazaki Hiroshi Miyazaki Masayuli Hiroi Manabu Tsujimura Nohjung Kwak Hyeon Deok Lee Yuji Awano Sibaim Kim Lucile Arnaud JD Luttmer Sitaram Arkalgud Azad Naeemi Dirk Gravesteijn NS Nagaraj Mike Mills Larry Smith Skip Berry Gunther Schindler Chung-Liang Chang Tomoji Nakamura Shuhei Amakawa Christopher Case Partial List of Contributors

3. Technology Drivers Expanding • Traditional geometric scaling • Cost. • Necessary to enable transistor scaling. • Performance • Dielectric constant scaling for delay, and power improvements. • Reliability • EM. • Crosstalk. • Increasing value by adding functionality using CMOS-compatible solutions: • Contributing to More than More: 3D integration of digital/analog flows, optical components, CNT-based sensors. • Will monitor product examples.

4. Proposed changes: update interconnect wiring definitions • Considering changes to interconnect wiring classification to better recognize current industry trends. • Target is 2009 roadmap edition.

5. 2008 Low-k update • Initiated effort to refine bulk dielectric constant. • Considering replacement of the range for bulk k by a single value.

6. 2008 Jmax updates • Model methodology was discussed. Will consider refining a few assumptions. • Currently revising two key inputs to Jmax models: critical wire lengths, load assumptions. • Validating technology maturity color shading

7. Planned roadmap updates DRAM • Appearance of overlapping metrics in FEP and interconnects • Japan Interconnect TWG and FEP will coordinate the matching • Considering increasing the 2009 low k value from 3.1-3.4 to 3.6 to 4.1 (shifted roadmap by 1 year).

8. Cross TWG meetings Design TWG (ad-hoc meeting) • Kicked off a collaborative effort to assess requirements on 3D interconnect process parameters by product drivers. • Focus: 2009 edition Test TWG • Initiated a collaborative effort with the Test TWG to include test challenges for 3D. • Focus: 2009 edition Assembly and Packaging TWG • Initiated effort towards alignment of definitions of key Through-Si via parameters, with the goal of avoiding reader confusion

9. Cross TWG meetings ERM TWG • Refined expected introduction of novel interconnect materials based on technical feasibility (Novel Macromolecules, Self Assembled Materials, CNT, nanowires, graphene). Focus: 2008 update. Modeling TWG • Revised with Modeling TWG key interconnect challenges. Focus: 2009.

10. Summary • Reviewing key interconnect parameters for the 2008 roadmap update. Expect minor changes. • Initiated key inter-TWG collaboration focusing on the 2009 roadmap edition.