1 / 7

Interconnect Working Group

Interconnect Working Group. 2008 Draft Edition 16 July 2008 SEMICON San Francisco Christopher Case, Didier Louis, Mauro Kobrinsky, Thomas Toms, Osamu Yamazaki, Shuhei Amakawa, Larry Smith, Eric Beyne, Scott List, Harold Hosack. Technology Requirements. Now restated and organized as

valiant
Download Presentation

Interconnect Working Group

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Interconnect Working Group 2008 Draft Edition 16 July 2008 SEMICON San Francisco Christopher Case, Didier Louis, Mauro Kobrinsky, Thomas Toms, Osamu Yamazaki, Shuhei Amakawa, Larry Smith, Eric Beyne, Scott List, Harold Hosack

  2. Technology Requirements • Now restated and organized as • General requirements • Resistivity • Dielectric constant • Metal levels • Reliability metrics • Level specific requirements (M1, intermediate, global) • Geometrical • Via size and aspect ratio • Barrier/cladding thickness • Planarization specs • Materials requirements • Conductor effective resistivity and scattering effects • Electrical characteristics • Delay, capacitance

  3. 2008 Low k update • For those who think changes in k of 0.1 are significant – we aim to please • For those who don’t – try reaching consensus on low k with 100 people • Proliferation of air-gap approaches • Values of effective k-value down to 1.7 with low crosstalk levels • Localized air gaps to maintain good thermal and mechanical properties

  4. 2008 Barrier/Nucleation/Resistivity • ALD barrier processes and metal capping layers for Cu are lagging in introduction • Resistivity increases due to scattering and impact of liners • No known practical solutions

  5. Processor Radio Memory Power Sensor Actuator More Moore More than Moore More than Moore – enabling functionality with CMOS compatibility • Path to functional diversity • Mixed technologies • Si, GaAs, HgCdTe together • Mixed signalling approaches • Optical and RF • Passive devices • Intelligent Interconnect (active devices, sensors, MEMS, biochips, fluidics, etc. in interconnect) • Repeaters in interconnect, combined metallic/semiconducting CNT interconnects • Back-end memory • Variable resistor via

  6. High Density TSV Roadmap or“enabling terabits/sec at femtojoules” • The Interconnect perspective - examples: • High bandwidth/low energy interfaces between memory and logic • Heterogeneous integration with minimal parasitics (analog/digital, mixed substrate materials, etc.) • “Re-architect” chip by placing macros (functional units) on multiple tiers (wafers) and connect using HD TSVs • Model assumptions: • TSV diameter limited by silicon thickness and TSV Aspect Ratio: • Pitch limited by TSV diameter, misalignment tolerance, minimum pad spacing

  7. DRAFT HD TSV Roadmap • Represents devices that could appear in production, using at least one approach to 3D integration • ≤10 mm Si thickness, wafer-to-wafer integration, wafers thinned after bonding

More Related