Interconnect Working Group

1. Interconnect Working Group 2011 Revision 13 July 2011 San Francisco USA Christopher Case

2. ITWG Regional Chairs Europe Hans-Joachim Barth Alexis Farcy Korea Hyeon-Deok Lee Sibum Kim US Christopher Case Japan Akira Matsumoto Tomo Nakamura Taiwan Douglas CH Yu

3. Partial List of Contributors Nobuo Aoi Sitaram Arkalgud Lucile Arnaud Koji Ban Hans-Joachim Barth Eric Beyne Boyan Boyanov Christopher Case Chung-Liang Chang Hsien-Wei Chen Gilheyun Choi Jinn-P. Chu Mike Corbett Alexis Farcy Paul Feeney Takashi Hayakawa Cheng-Chieh Hsieh Masayoshi Imai Atsunobu Isobayashi Raymond Jao Shin-Puu Jeng Ajey Joshi Morihiro Kada Sibum Kim Nobuyoshi Kobayashi Mauro Kobrinsky Kaushik Kumar Nohjung Kwak Hyeon Deok Lee Scott List Anderson Liu Didier Louis Toshiro Maekawa David Maloney Akira Matsumoto Azad Naeemi Mehul Naik Tomoji Nakamura • Yuichi Nakao • Akira Ouchi • Roger Quon • Rick Reidy • Scott Pozder • Larry Smith • Mark Scannell • Hideki Shibata • Michele Stucchi • Wen-Chih Chiou • Weng Hong Teh • Thomas Toms • Manabu Tsujimura • Kazuyoshi Ueno • Osamu Yamazaki • Paul Zimmerman • 0711 - 3 -

4. Interconnect scope Conductors and dielectrics Starts at contacts Metal 1 through global levels Includes the pre-metal dielectric (PMD) Associated planarization Necessary etch, strip and cleans Embedded passives Global and intermediate TSVs for 3D Reliability and system and performance issues “Needs” based replaced by – scaled, equivalently scaled or functional diversity drivers.

5. Wire Wire Wire Metal 3 Via Via Via Metal 2 Metal 1 Metal 0 Poly Pitch Metal 1 Pitch Metal 1 Pitch Metal 1 Pitch Hierarchical Cross Sections Passivation Dielectric Etch Stop Layer Global (=IMx1.5~2µm) Dielectric Capping Layer Global (=IMx1.5~2µm) Copper Conductor with Barrier / Nucleation Layer Semi- Global (=M1x2) Inter- Mediate (=M1x1) Inter- Mediate (=M1x1) Tungsten Contact Plug Metal 1 Metal 1 Pre-Metal Dielectric Flash Cross-Section ASIC Cross-Section MPU Cross-Section • MPU: Revised hierarchy • ASIC: No drastic change, however semi-global should be kept at 2 x M1 • Flash: The new technology driver for M1

6. Technology Requirements Now restated and organized as General requirements Resistivity Dielectric constant Metal levels Reliability metrics Level specific requirements (M1, intermediate, global) Geometrical Via size and aspect ratio Barrier/cladding thickness Planarization specs Materials requirements Conductor effective resistivity and scattering effects Electrical characteristics Delay, capacitance, crosstalk, power index

7. Technology Drivers Expanding Traditional geometric scaling Cost Necessary to enable transistor scaling Performance Dielectric constant scaling for delay, and power improvements Reliability EM Crosstalk Increasing value by adding functionality using CMOS-compatible solutions: 3D, optical components, sensors Contributing to More than Moore

8. Difficult challenges (1 of 2) Meeting the requirements of scaled metal/dielectric systems Managing RC delay and power New dielectrics (including air gap) Controlling conductivity (liners and scattering) Filling small features Barriers and nucleation layer Conductor deposition Reliability Electrical and thermo-mechanical Engineering a manufacturable interconnect stack compatible with new materials and processes Defects Metrology Variability

9. Difficult challenges (2 of 2) Meeting the requirements with equivalent scaling Interconnect design and architecture (includes multi-core benefits) Alternative metal/dielectric assemblies 3D with TSV Interconnects beyond metal/dielectrics 3D Optical wiring CNT/Graphene Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system Non-traditional materials (for optical, CNT etc.) Unique metrology (alignment, chirality measurements, turning radius etc)

10. HistoricalTransitionofITRSLow-kRoadmap ITRS2003 ITRS2011 ITRS2005 ITRS2007-2010 Effective Dielectric Constant; keff ITRS2001 Before 2001, unreasonable RM without logical basis ITRS1999 Year of 1st Shipment Narrowed effective range due to elimination of hybrid stack 2009 Summer Conference

11. 4.0 3.5 3.0 Effective Dielectric Constant; keff 2.5 2.0 1.5 1.0 2011 Low-k Roadmap Update for MPU/ASIC Calculated based on delay time using typical critical path ITRS2009 2.8-3.2 Estimated by typical three kinds of low-k ILD structures ITRS2009-10 ITRS2007-8 ITRS2011 2.5-3.00 2.4-2.8 2.1-2.5 1.9-2.3 Delay time improvement by 20% Manufacturable solutions are known Manufacturable solutions exist, and are being optimized Red Brick Wall (Solutions are NOT known) 18 19 20 11 12 13 14 15 16 17 21 22 23 Year of 1st Shipment

12. 2011 Low-k Roadmap Update for MPU/ASIC • Air gap architectures will be required forkeff£ 2.0 • No viable materials expected to be available. • Mechanical requirements easier to achieve with air-gaps. • End of the material solution and the beginning of an architecture solution.

13. Air Gap • Approaches • Creation of air gaps with non-conformal deposition • Removal of sacrificial materials after multi-level interconnects Pictures (top left, clockwise): NXP, IBM, Panasonic, TSMC

14. Flash Application K.Prall et al., (Micron & Intel), “25 nm 64Gb MLC NAND Technology and Scaling Challenges”, Tech. Dig. of IEDM2010, pp.102-105 (2010). Fig. 6 Cross-section of the cell in the WL direction showing the WL airgap and reduction in total FG-FG couplingwith airgap (red square) and without (blue diamond). WL bending is caused by sample preparation. A 25% reduction in total interferenceis achieved with the airgap. Fig. 7 Cross-section of the cell in the BL direction showing the bit line airgap. A 30% reduction in BL capacitancewas achieved.

15. Flash interconnect requirements • Items in the table • Flash half pitch (nm) • DRAM half pitch (nm) • MPU/ASIC half pitch (nm) • Numbers of metal layers • Metal 1 wiring ½ pitch (nm) • Interlevel metal 1 insulators – max. effective dielectric constants • Interlevel metal 1 insulators – min. effective dielectric constants • Metal 1 A/R • Conductor effective resistivity (µcm) for Cu • Specific via resistance (cm2) • Contact A/R • Specific contact resistance (cm2)

16. 2011 Barrier/Nucleation/Resistivity • Barrier layer requires an appropriate combination of liners and nucleation layers potentially with ALD, and considering low k properties. • Resistivity increases due to scattering and impact of liners • No known practical solutions

17. Wire current limit – width dependence Jmax On chip local clock frequency 2010 Update 2010Update 2011 Revision 2011 Revision JEM • Jmax will increase with frequency and reducing cross-section, while JEM will scale with the product w*h according to EM lifetime dependence on wiring width. The color boundaries may actually be width-dependent. • Jmax is relaxed mainly due to the reduction of clock frequency. • JEM (J limited by EM) is considered to have been improved by EM enhancement technologies such as CuAl and CoWP cap.

18. Metal Capping ＜CuGeN-Cap＞ Ge Ge Ge Ge Al Al Al Al Al Al Al Al Al Al Al Al Al Al Al Al Various lifetime improvement approaches against the resistivity increase ＜CoWP, or CVD-Co-Cap＞ CuSi(N) + Ti-BM CuAl ＜CuSiN-Cap＞ Si Si Si Si Si Si Si CuSiN（2） Si Si Si Si Si Si CoWP EM Lifetime Improvement Ratio ＜CuAl-Alloy＞ CuSiN（1） CuSiN CuGeN ＜CuSiN-Cap+Ti＞ Normalized Resistance Increase Ratio H. Shibata added published data based on Yokogawa et. Al. IEEE Trans on ED.2008

19. High Density TSV Roadmap or“enabling terabits/sec at femtojoules/bit” The Interconnect perspective - examples: High bandwidth/low energy interfaces between memory and logic Heterogeneous integration with minimal parasitics (analog/digital, mixed substrate materials, etc.) “Re-architect” chip by placing macros (functional units) on multiple tiers (wafers) and connect using HD TSVs Defined a 3D interconnect hierarchy TSV dimensions Minimum contact pitches Overlay accuracy Described process modules

20. Emerging Interconnect Changes • Current focus is on transport properties of Cu replacements, optical and native device interconnects • Research focus in optical in on die-to-die and chip-chip as the most probable commercial intercept • Rate of introduction of new candidates in research is decreasing  topological insulators is the only 2011 addition • Key messages: • Novel state variables are slow relative to repeater-driven Cu/low-k and require significant area savings to maintain switching speed • Evaluation of energy efficiency of emerging options necessitates joint consideration of switch and interconnect options - 21 -

21. All roads lead to C?

22. New Emerging Interconnect Summary Table - 24 -

23. Topological Insulators – an interconnect option beyond Cu/Low k? • Potential • Graphene-like electron transport • Elastic scattering protection • Spin-polarized transport • Device/interconnect synergy • Cons • Loss of scattering immunity due to layer-to-layer coupling and inelastic scattering S. Zhang, Physics (2008) Prognosis: unlikely to be feasible as conventional interconnect but holds potential for spintronics J.Seo, Nature(2010)

24. Delay of New State Variables Diffusion Diffusion Spin Waves (105 m/s) Spin Waves (104 m/s) Drift, 0.8V Spin Waves (105 m/s) Delay (ps) Needed Area Scaling ACMOS /Aemerging Ballistic Ballistic Drift CMOS (5x Driver) Interconnect Length (Gate Pitch) Interconnect Length (Gate Pitch) New state variables are slow compared to conventional CMOS interconnects and must enable substantial area savings to match CMOS performance

25. Interconnect Summary 2011 Low-k – slightly changed Air gaps expected to be solution for keff£2.0 First implementation will be for Flash Jmax current limits updated with relaxed on-chip clock frequency Moves red zone by one to two years Barriers and nucleation layers are a critical challenge ALD integration is still being investigated including the combination with appropriate dielectrics and barrier metals. Approaches of new liners (Co, Ru and others) stacked with barrier layers are proliferating Capping metal for reliability improvement nearing production Revised 3D TSV roadmap tables Emerging interconnect solutions are being developed. All new interconnect variables are slow and will require substantial area savings to match/exceed the speed of repeated Cu/low-k with CMOS drivers; applications will likely be driven by new functionality enabled by emerging interconnects Novel state variables are slow relative to repeater-driven Cu/low-k and require significant area savings to maintain switching speed Evaluation of energy efficiency of emerging options necessitates joint consideration of switch and interconnect options - 27 - - 27 -