Interconnect Working Group

1. Interconnect Working Group ITRS 2004 14 July 2004 San Francisco Christopher Case, Harold Hosack, Kazuyoshi Ueno, Osamu Yamazaki, Ken Monnig, Bob Geffken, Skip Berry, Jeff Wetzel

2. ITWG Regional Chairs Japan Manabu Tsujimura Hideki Shibata Taiwan Douglas CH Yu US Robert Geffken Christopher Case Europe Hans Joachim-Barth Joachim Torres Korea Hyeon-Deok Lee Hyun Chul Sohn

3. Agenda • Interconnect scope • Highlight of changes • Difficult challenges • Review of key issues on materials • Reliability • Technology requirements issues • Table updates • Interconnect performance • Last words

4. Interconnect scope • Conductors and dielectrics • Metal 1 through global levels • Starts at pre-metal dielectric (PMD) • Associated planarization • Necessary etch and surface preparation • Embedded passives • Reliability and system and performance issues • Ends at the top wiring bond pads • Predominantly “needs” based, with some important exceptions (k and resistivity)

5. Typical MPU cross section Passivation Passivation Dielectric Dielectric Wire Wire Etch Stop Layer Etch Stop Layer Via Via Global (up to 5) Global (up to 5) Dielectric Capping Layer Dielectric Capping Layer Copper Conductor with Copper Conductor with Barrier/Nucleation Layer Barrier/Nucleation Layer Intermediate (up to 8) Intermediate (up to 8) Metal 1 Metal 1 Pre Metal Dielectric Pre Metal Dielectric Tungsten Contact Plug Tungsten Contact Plug Metal 1 Pitch Metal 1 Pitch

6. 2004 highlights • Changes to low k dielectric roadmap • Updated wiring performance metrics to include impact of scattering • New metrics which calculate impact at Metal 1, intermediate and global wiring • Updated the RC per unit length figure of merit and Line length (mm) where t = RC delay (Metal 1 wire) with scattering • Updated Jmax specification for MPU • Updated contact and via resistivity for DRAM

7. Introduction of new materials to meet conductivity requirements and reduce the dielectric permittivity* Engineering manufacturable interconnect structures compatible with new materials and processes* Achieving necessary reliability Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required to achieve necessary circuit performance and reliability. Manufacturability and defect management that meet overall cost/performance requirements Mitigate impact of size effects in interconnect structures Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required. Patterning, cleaning, and filling at nano dimensions Integration of new processes and structures, including interconnects for emerging devices Identify solutions which address global wiring scaling issues* Difficult Challenges >45 nm <45 nm * Top three grand challenges

8. Materials Challenges • Near and long term – size effects • Microstructural and atom scale effects • Continued introduction of materials • barriers/nucleation layers for alternate conductors - optical, low temp, RF, air gap • alternate conductors, cooled conductors • More reliability challenges

9. Reliability Challenges • Short term • New failure mechanisms with Cu/low k present significant challenges before volume production • Electrical, thermal and mechanical exposure • interface diffusion • interface delamination • Higher intrinsic and interface leakage in low k • Need for new failure detection methodology to establish predictive models

10. Attaining Dimensional Control • 3D CD of features • Multiple levels • performance and reliability implications • reduced feature size, new materials and pattern dependent processes • Process problems • Line edge roughness, trench depth and profile, via shape, etch bias, thinning due to cleaning, CMP effects. • Process interactions • CMP and deposition - dishing/erosion - thinning • Deposition and etch - to pattern multi-layer dielectrics • Patterning, cleaning and filling at nano dimensions • particularly DRAM contacts and dual damascene

11. Technology Requirements • Wiring levels including “optional levels” • Reliability metrics • Minimum wiring/via pitches by level • Performance metric • Planarization requirements • Conductor resistivity • Barrier thickness • Dielectric metrics including effective k

13. MPU HP Near Term Years Cu at all nodes - conformal barriers – resistivity 2.2 mW-cm

14. Dielectric Updates Proposal from Japan TWG on Low-k roadmap color revision Not changed

15. DRAM Small changes in specific via and contact resistivity Contact A/R rises to >20 in 2018 - a red challenge - associated with 16 nm DRAM half pitch Low k in 2003 - Cu delayed to 2007 Identified need to distinguish embedded, flash, and traditional DRAM

16. DRAM Updates <contact and via structure> Contact n+-----W/TiN/Ti p+-----W/TiN/Ti Via-hole W/TiN on W (untill 2006) Cu/Ta on W (beyond 2007) From 2003-2006, actual data measured using 110-90nm DRAM contact/via structures were adopted as the table value. And beyond 2007, required values for reducing contact/via resistivity by 30% for 2 years were described.

17. p=0(complete diffuse scattering) 5 p=0.3 Measured Cu resistivity without BM Updated(May2004) 4 ρ(Al):2.74μΩcm 3 Resistivity(μΩcm) 2 p=0.5 1 0 0 100 200 300 400 500 Wire width(nm) Cu Wire Resistivity Increase by Electron-scattering Effect From Leti Arnaud-san New experimental results calculated with ρo = 1.8 μΩcm, λ = 40 nm, p= 0.6, r= 0.2 Experimental results shown at IITC 2003 p. 133

18. ρ and ρeff Calculation Result for M1 Wire Level for Every Year

19. Surface preparation • Cross TWG work from FEP • Technology requirements address: • Killer defect density and size • Back surface particles • Metallic and organic contamination • Dielectric constant change (increase) due to stripping, cleaning and rework

20. Technology Requirements Near Term: Modifications of Low-k Material and CD Metrics Dielectric Constant Delta: Take into Account Total Clean Process Add Profile Change as Metric

21. Technology Requirements Near Term: Post-CMP Cleaning Metrics New Format Proposed with Focus on Post-CMP Clean Watermarks and Surface Roughness of Cu Included

22. Cross TWG Issues • Metrology • Desire to refine and understand void specification in Cu (1% of total volume of Cu) • Can’t measure – is the requirement realistic • 3D CD needs discussed at great length, including line and sidewall roughness – need metric, including damage due to processing and impact on effective k • Factory Integration • Need to reduce N2 and NF3 (cost driver) • Cu/low k contamination of FOUPs – what other materials are an issue (eg Pt, Ir, PZT) • Increased power and cooling for PVD and etch tools • Yield Enhancement – Share contamination and purity specs for many fluids and precursors, slurry characterization, what are AMC specs for Cu technology? • ESH • Clarification of dilute Cu waste stream reclaim/recovery • Same need on N2 and NF3 • A&P • Interconnect will provide mechanical properties of dielectric stack • Test – concerns over mechanical damage to weaker dielectrics from probing • FEP –nothing significant • 3D IC XTWG - Dialog started with Design, A&P and Test to identify directions for 3D ICs – may address global wiring problem

23. Modulus vs k-value Low-k materials from Applied Materials, ASM, Dow Chemical, Honeywell, JSR, Novellus

24. Global interconnect roadmap

25. 2005 Thoughts • Metal 1 design rule concerns • Resolved confusion over non -contacted versus contacted half-pitch and the incorrect use of technology node for MPU • Recent publications suggest M1 scaling may be accelerating • Desirable to have separate tables for high performance • High performance MPU pitches scaling at ~0.7/3 years • High performance ASIC pitches scaling at ~0.75-0.8/ 2 years • Decoupled from DRAM at 0.7/3 years • Dialog started with Design, A&P and Test to identify directions for 3D ICs – may address global wiring problem

26. Last words • Continued changes in materials • Develop solutions for emerging devices • Must manage 3D CD • System level solutions must be accelerated to address the global wiring grand challenge • Cu resistivity increase impact appears ~2006 • materials solutions alone cannot deliver performance - end of traditional scaling • integrated approach with design and packaging