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High Speed Serial Link Data Characteristic Influence Over Lock Time Full Integrated Experiment

High Speed Serial Link Data Characteristic Influence Over Lock Time Full Integrated Experiment. Final Presentation. Yifat Kuttner & Noam Gluzer. Supervisor: Boaz Mizrachi. Winter 2004/5 – single semester. Outline. Project goals Introduction System overview Additions and adjustment

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High Speed Serial Link Data Characteristic Influence Over Lock Time Full Integrated Experiment

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  1. High Speed Serial Link Data CharacteristicInfluence Over Lock Time Full Integrated Experiment Final Presentation Yifat Kuttner & Noam Gluzer Supervisor: Boaz Mizrachi Winter 2004/5 – single semester

  2. Outline • Project goals • Introduction • System overview • Additions and adjustment • Issues encountered • Results • Summary

  3. Project Goals • Implementing an experiment that demonstrates the effects of physical and data characteristics, on a receiver locking time. • The experiment is based on an existing system.

  4. Introduction Lock mechanism • Clock and data are transmitted on the same channel • The receiver reconstructs the clock to the right rate and phase • When the clock is correctly reconstructed, the data can be sampled with it • In this state, the receiver is "Locked" on the incoming signal • Lock success and speed are affected by characteristics of the physical link and the transmitted data • This experiment demonstrate these effects

  5. System overview • The system consists of two boards: • FPGA evaluation board, which generates and analyzes data traffic • High Speed Serial Data Channels board (HSDC), which routes this traffic through different physical links • The boards are PC-controlled, using a dedicated programs

  6. Simplified Hardware Description

  7. Lock Time Experiment • Data is transmitted from the FPGA to the HSDC board • Lock Time is measured from the start of data transmission, until the 4x4 switch's CDR indicates lock • The time is measured by counting 100MHz clocks

  8. “Traces” Experiment • Data is transmitted from the FPGA to the HSDC board • The data is routed through different traces to demonstrate gradual degradation in the received data, until lock cannot be achieved • This degradation can be visually seen on an oscilloscope

  9. Additions and Adjustments HSDC Board • Connectors and pull-up resistors were added to the Lock signals FPGA Board • Inputs for the Lock signals were added • Data generator module was adjusted to cyclic transmitting 40-bit data, as given by the user, with no 8/10 automatic encoding • Data analyzer module was adjusted to display this experiment results in the PC software • Counter module was added

  10. Encountered Issues HSDC - Faulty Lock signal in one of the boards (s/n 4) Faulty 4x4 switch inputs (Input 0 on board 4, Input 1 on board 2) Noisy Lock signal for data input of DC

  11. Trace 7 Some Results …. Data :0011101110110001000100111011101100010001 Lock time : ~ 402542 ticks

  12. Trace 9 Lock time : ~ 2819705 ticks

  13. Trace 10 No Lock

  14. Summary • This experiment will be added alongside the existing one, extending it with the following supplements: • Showing how traces can damage a link, from slower lock time to inability to lock at all. • Showing the role of coding in improving link robustness • The link degradations can be seen quantitatively and visually

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