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Test Chip Experiments at Stanford CRC

C. enter for. R. eliable. C. omputing. Test Chip Experiments at Stanford CRC. ITC 2009 Presenter: James C.M. Li Ahmed Al-Yamani, Jonathan Chang, Piero Franco, Siyad Ma, Subhasish Mitra, Intaik Park, Chao-wen Tseng, Erik Volkerink. CRC Test Chip Experiments. Objective:

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Test Chip Experiments at Stanford CRC

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  1. C enter for R eliable C omputing Test Chip Experiments at Stanford CRC ITC 2009 Presenter: James C.M. Li Ahmed Al-Yamani, Jonathan Chang, Piero Franco, Siyad Ma, Subhasish Mitra, Intaik Park, Chao-wen Tseng, Erik Volkerink

  2. CRC Test Chip Experiments • Objective: • Evaluate effectiveness of different test techniques • test sets, test conditions, fault model, IDDQ … • Features: • Real defects in production • Spans many technology nodes (0.7 to 0.13m) • 18-year old • One of the most famous test chip experiments in test community • 30+ technical publications • Impacts both test industry and research • VLV, N-detect, TARO …

  3. The Murphy Chip • Started 1991 • Designed by Hughes and fabricated by LSI Logic • 0.7m gate array technology • 25K gates, 4 copies of 5 combinational cores • A total of 4.5K chips were tested

  4. Designed by CRC and fabricated by LSI logic 0.35m standard cell technology 6 cores, 265K gates 2 processors and 4 combinational cores A total of 9.6K chips were tested The ELF35 Chip

  5. The ELF 18 chip by Philips 0.18m technology 26 cores, including memories, analog circuits, and REAL digital signal processors More than 70K chips were tested The ELF13 Chip by Nvidia Graphic processor 0.13m , 7.2 million logic gates more than 10 different clock domains The Other ELF Chips

  6. Highly Cited Papers • An experimental chip to evaluate test techniques experiment results [ITC ‘95] • 193 citations • Very-low-voltage testing for weak CMOS logic ICs [ITC’93] • 119 citations • Stuck-fault tests vs. actual defects [ITC ‘00] • 100 citations • Multiple-output propagation transition fault test [ITC ‘01] • 61 citations • Testing for resistive opens and stuck opens [ITC’01] • 46 citations • google scholar as of Oct., 2009

  7. Key Impacts on Test Techniques • Very-low Voltage Testing • N-detect test patterns • TARO test patterns • Gate exhaustive test patterns

  8. Former students: Ahmed Al-Yamani, Jonathan Chang, Piero Franco, Donghwi Lee, Jaekwang Lee, James Li, Siyad Ma, Subhasish Mitra, Intaik Park, Chao-wen Tseng, Erik Volkerink, … Acknowledgements (1)

  9. Acknowledgements (2) • Manufacturers: Cisco, Intel, LSI logic, Nvidia, Philips, … • EDA companies: Cadence, Mentor Graphics, Synopsys, and Syntest,…. • ATE companies: Advantest USA, Credence, Verigy,… • Test engineers: Mike Purtell, and many more others …. • We apologize if we miss your names

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