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Connect Four Project

Connect Four Project. Fall 2011 Anna Grimley & Josh Mandich Lab Section: F. Connect Four Game. Objectives Create Verilog Code for Connect Four Logic Synthesize Code Create Layout. Project Constraints. Game as Two Players Must use 4x4 matrix of LED’s

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Connect Four Project

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  1. Connect Four Project Fall 2011 Anna Grimley & Josh Mandich Lab Section: F

  2. Connect Four Game Objectives • Create Verilog Code for Connect Four Logic • Synthesize Code • Create Layout

  3. Project Constraints • Game as Two Players • Must use 4x4 matrix of LED’s • Player must be able to start by using the START input • PONE always starts, PONE&PTWO can not give input simultaneously • Player must be able to start by using the START input • Other times to think about • Must not allow a player to overwrite previous selection. • Must not allow player to play out of turn • Game must stop when player wins • A 4x4

  4. Strategy • Keep code simple • Take into consideration what is synthesizable and what is not • Start building code early and seek for help Truly elegant design incorporates top-notch functionality into a simple, uncluttered form. — David Lewis

  5. Verilog HDL • At Start==0 sets all registers to 0. and turn=1 • Continues to check PONEWIN & PTWOWIN are zero at all steps

  6. Verilog Code Input and Start

  7. Verilog Code Light LED from User Input

  8. Verilog Code Detect Winning Input

  9. Testing Verilog Code Test Bench • Wanted to Test Player can not keep playing when LED already selected • Proved that PONEWIN would work when PONE had won

  10. VSIM Testbench Output

  11. Synthesizing Schematic of elaborated Verilog Connect 4. (Code in RTL compiler)

  12. Synthesizing Schematic of Optimized Connect 4 (Code integrated with OSU lib)

  13. Synthesizing Schematic of Optimized Connect 4 (Code integrated with OSU lib)

  14. Synthesizing Schematic cell view of synthesized Connect4 code in Virtuoso

  15. Layout Initial Floor Plan Floorplan layout with power rings

  16. Layout Cell and IO pin Placemnent

  17. Layout Power and Ground Routing Power Routing between die I/O and standard cells

  18. Layout Final layout view of Connect4.v in Encounter with filler added Yay! Celebrate!!!

  19. Final Layout Using OSU_stdcells_ami05 library.

  20. Major Take Away’s • Understand what verilog can be synthesized and what can not • Keep Verilog simple • Be patient with synthesizing and layout in encounter/virtuoso • Spending time on HDL pays off in synthesizing

  21. Ha HaHa Not this Connect Four

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