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Status of the SRS Hardware and Performance

Check the latest developments and performance metrics of SRS hardware components presented by Sorin Martoiu from CERN at the 6th RD51 Collaboration Meeting in Bari. Explore updates on FEC Cards, ADC C-Cards, APV Hybrids, firmware, and more.

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Status of the SRS Hardware and Performance

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  1. Status of the SRSHardware and Performance Sorin Martoiu, CERN PH/DT Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  2. SRS APV DAQ Chip Carriers Single Master Slave • Hardware Status • FEC Card • ADC C-Card • APV Hybrid • Firmware and DAQ • Overview and Current Status • UDP Data Transfer • DAQ software • Conclusions • Next Steps • SRU status • FEC upgrade • Advanced Firmware modules • Other chips/applications Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  3. SRS FEC Card Chip Carriers Single Master Slave • Designed and realized at the Polytechnic University of Valencia (J.Toledo – see following talk) • Virtex LX50T FPGA • A/B extension interface (PCIE conn) • 20 differential • 48/24 single-ended/diff • 2 x I2C, 1 x JTAG • 2 x 3.75Gbps RocketIO GTP transceivers • 200 MHz local clock oscillator • 1Gb DDR2 RAM, 1kb GP FLASH • SFP/Gb Ethernet/DTC interface • NIM/LVDS GPIO • Power control and distribution ; HV feed-through Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  4. SRS ADC C-Card Chip Carriers Single Master Slave • 2 x 12-Bit Octal-Channel ADC • up to 50(65) MSPS • Programmable Gain: 0dB to 12dB • Low-Frequency Noise Suppression • 8 x HDMI channels • 2 analog channels (differential) with variable equalization • 1 x I2C, 1 x CMOS (rst) • 2 x LVDS OUT (clk, trg), 1 x LVDS in • Tailored for APV25 or Beatle FE chips • compatible with other analog FE (see next talks) • Power and equalization control • Slow control mux/switch • Clock distribution • Temperature/Voltage Monitoring Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  5. ADC C-CardPerformance @ 40 MHz noise  0.63 ADC bins (rms)  300 uV (rms) Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  6. ADC C-CardPower Consumption Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  7. SRS APV Hybrid Chip Carriers Single Master Slave • APV25 front-end • 128 channels • analog sampling memory (192s/ch) • current-mode differential serial analog output • Discharge protection • Power regulation • Clock PLL/trigger decode Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  8. SRS APV Hybrid v2 Chip Carriers Single Master Slave • smaller HDMI connector • improved manufacturability • low-noise power regulators • common-mode fix Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  9. APV Hybrid Overview Discharge protection (NUP4114) Power regulators (MAX8556) • HDMI connector • power • clock/trigger • analog signals • I2C • Coax Connectors • <2mohm GND • mechanical PLL25 rad-hard chip clock/trigger • APV25 chip • 128 channels • 192-deep analog sampling memory Extension connector for a second APV25 Hybrid Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  10. SRS APV HybridManufacturability The two vias in the bonding region eliminated to improve manufacturability APV Hybrid v1 APV Hybrid v2 Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  11. SRS APV HybridManufacturability • 50mm x 68mm form factor • 4 layers PCB/capton • 1 mm thickness • Manufacturability issues: • chemical etch • clearance < 50 um in the bond-pad region • still waiting for production quotes Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  12. SRS APV HybridPerformance APV Hybrid V2 – noise APV Hybrid V1 – noise Avg ENC = 356 el Avg ENC = 307 el • Bench performance (no detector) • More on performance with GEM detectors in Kondo’s talk Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  13. SRS APV HybridCommon-Mode Problem APV Hybrid V1 – raw analog stream APV Hybrid V2 – raw analog stream Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  14. SRS APV HybridCommon Mode Correction Offline common-mode correction APV Hybrid V1 – Signal Fit APV Hybrid V1 – Signal Fit Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  15. Firmware and DAQ • Hardware Status • FEC Card • ADC C-Card • APV Hybrid • Firmware and DAQ • Overview and Current Status • UDP Data Transfer • DAQ software • Conclusions • Next Steps • SRU status • FEC upgrade • Advanced Firmware modules • Other chips/applications Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  16. FirmwareOverview Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  17. FirmwareStatus CERN ? Valencia Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  18. SRS UDP data protocol UDP Layer Frame Counter FEC Layer Data Header Header Info* • Event is broken into a number of frames (MTU = 9kB) • Frame Counter used for fragment re-ordering and fragment loss detection • Data Header and Header Info identifies the data type, address, word packing, etc 1st frame Hybrid Layer Data Data … Data UDP Layer Frame Counter FEC Layer Data Header Header Info* 2nd frame Hybrid Layer Data Data … Data … … n x frames Event Trailer Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  19. DAQ Software • Labview DAQ: • laboratory based • monitoring and debugging • no proper DAQ (help welcomed) • DATE/AMORE: • full DAQ/monitoring system • separate slow control Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  20. Conclusions • First SRS system with 11 APV hybrids up and running taking cosmic data with GEM detector (see Kondo’s talk). • First SRS system running with PMTs and SiPMTs for NEXT experiment (see next talk) • 1Gb Ethernet-based readout with DATE. • Good performance and system stability. • SRU based scalar system will follow shortly • Other applications Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  21. Next Steps • Hardware Status • FEC Card • ADC C-Card • APV Hybrid • Firmware and DAQ • Overview and Current Status • UDP Data Transfer • DAQ software • Conclusions • Next Steps • SRU status • FEC upgrade • Advanced Firmware modules • Other chips/applications Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  22. SRU Status • 12 PCB’s manufactured • Assembly in preparation • Tests in ~ 6 weeks time Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  23. FEC Upgrade • Virtex 6 FPGA (built-in SEU protection, more resources, …) • A/B extension interface (PCIE conn) • 20 differential • 80/40 single-ended/diff • 2 x I2C, 1 x JTAG • 4x 5Gbps RocketIO GTP transceivers • 200 MHz local clock oscillator • DDR3 RAM (SO-DIMM?), 1kb GP FLASH • SFP+/5Gb Ethernet/DTC interface • NIM/LVDS GPIO • Power control and distribution ; HV feed-through Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  24. Advanced Firmware Modules • APV synchronization and sparse (pipelined) readout • Zero-suppression • Common-mode subtraction • Baseline correction • Fully-automatic initialization • Hybrid detection and synchronization • Cable-length (equalization) adjust • Dynamic range and polarity adjust • Partial reconfiguration – loading application code automatically when extension card (A/B/C-Card) is inserted Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  25. Other Chips/Application • Timepix/Medipix (Bonn) • MaMMA BNL chip (CERN, see Venetios’s talk) • GEMROC • VFAT – on-going discussion on availability (respin/redesign) Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  26. Backup Slides Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  27. Simplified Block Diagram C-type Card ADS5281 ADC_LVDS_7 ADC_IN_7 ADC_LVDS_6 ADC_IN_6 Receiver/Equalizer ADC_LVDS_5 ADC_IN_5 ADC_LVDS_4 ADC_IN_4 Receiver/Equalizer HDMI ADC_LVDS_3 ADC_IN_3 I2C Translator ADC_LVDS_2 ADC_IN_2 ADC_LVDS_1 ADC_IN_1 CLK/TRG Driver ADC_LVDS_0 ADC_IN_0 ADS5281 TO FPGA ADC_LVDS_7 ADC_IN_7 ADC_LVDS_6 ADC_IN_6 ADC_LVDS_5 ADC_IN_5 ADC_LVDS_4 ADC_IN_4 ADC_LVDS_3 ADC_IN_3 ADC_LVDS_2 ADC_IN_2 ADC_LVDS_1 ADC_IN_1 ADC_LVDS_0 ADC_IN_0 Receiver/Equalizer Receiver/Equalizer HDMI I2C Translator Control Monitor CLK/TRG Driver CLK/TRG Distribution I2C Switch Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

  28. Input Equalization APV25 Short Cable APV25 Long Cable • 4 equalization steps to accommodate cables up to 30 meters Status of the SRS, Sorin Martoiu (CERN), 6th RD51 Collaboration Meeting, Bari

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