1 / 4

Hardware status GOLD

Hardware status GOLD. Update 03 Mar. 2010. GOLD floor plan (approximate). Z3. L. 5 * XC6VLX ( L,M ) 4* XC6VHX ( H ) 144 multigigabit links in zone 2 (equiv. 22300 bit / BC). L. Opto. L. L. M. Z2. H. H. 890Gb/s total. H. H. Z1. GOLD – current status.

shyla
Download Presentation

Hardware status GOLD

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Hardware status GOLD Update 03 Mar. 2010

  2. GOLD floor plan(approximate) • Z3 • L • 5 * XC6VLX (L,M) • 4* XC6VHX (H) • 144 multigigabit links in zone 2 (equiv. 22300 bit / BC) • L • Opto • L • L • M • Z2 • H • H • 890Gb/s • total • H • H • Z1

  3. GOLD – current status • Schematics partially done • Routing as shown: • xGb/s links hand routed  • ‘Low’ speed links (1Gb/s) to be auto routed

  4. GOLD status • Schematics and layout under way • Components ordered. Lead time: • AVAGO (2*T, 2*R) : arrived • SNAP12 : mid April • Xilinx XCVLXT: 8-10 weeks • Production of Xilinx HXT devices delayed Firmware activities: Currently working on extension of VME bus from 9U processor crates, via BLT module, optically into GOLD

More Related