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PreSim CoreGenerator IP in ISE 5.1i with Verilog HDL

This tutorial provides step-by-step instructions on how to compile CoreGen library in ISE 5.1i using Verilog HDL.

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PreSim CoreGenerator IP in ISE 5.1i with Verilog HDL

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  1. PreSim CoreGenerator IP in ISE 5.1i with Verilog HDL Chih-Peng Fan

  2. Step 1. Compile CoreGen libarary compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libs Chih-Peng Fan

  3. Step 2. Create CoreGen libarary Verilog lib Chih-Peng Fan

  4. Step 3. Run Xilinx CORE Generator Chih-Peng Fan

  5. Step 4. Choose Multiplier IP Chih-Peng Fan

  6. Step 5. Create files from CORE Generator *.v is the key Chih-Peng Fan

  7. Step 6. Prepare a top file for mult8x8.v(from CoreGen) Top_mult8x8.v module Top_mult8x8(a,b,o); input [7:0] a,b; output [15:0] o; // ----- Begin Cut here for INSTANTIATION Template --- // INST_TAG mult8x8 ttt ( .a(a), .b(b), .o(o)); // INST_TAG_END endmodule Chih-Peng Fan

  8. Step 7. Prepare files for Pre-simulation Chih-Peng Fan

  9. Step 8. Run ModelSim, then change the directory Chih-Peng Fan

  10. Step 9. Create a New Library Chih-Peng Fan

  11. Step 10. Create a New Project Chih-Peng Fan

  12. Step 11. Add source *.v files in the Project Chih-Peng Fan

  13. Step 12. Compile all *.v files Chih-Peng Fan

  14. Step 13. Run Simulate … Chih-Peng Fan

  15. Step 14. Add simulation library Chih-Peng Fan

  16. Step 15. Load the simulation module Chih-Peng Fan

  17. Step 16. Create a waveform window Chih-Peng Fan

  18. Step 17. Generate the waveform Chih-Peng Fan

  19. test_mult8x8.v `timescale 1ns / 100ps module stimulus; reg[7:0] A,B; wire[15:0] PRODUCT; reg CLK; reg Reset; reg [15:0] D_PRODUCT; reg [7:0] IN_A [3:0]; reg [7:0] IN_B [3:0]; reg [1:0] index; // -------------------------------- Top_mult8x8 mult2 (A,B,PRODUCT); // ------------------------------- always #10 CLK=~CLK; initial begin Reset=1'b0; CLK=1'b0; #25 Reset=1'b1; end ………… …………. …………. Chih-Peng Fan

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