Progress towards a Long Shaping-Time Readout for Silicon Strips

1. Progress towards a Long Shaping-Time Readout for Silicon Strips Bruce Schumm SCIPP & UC Santa Cruz Cornell LC Workshop July 13-16, 2003

2. The SD Tracker

3. Tracker Performance SD Detector burdened by material in five tracking layers (1.5% X0 per layer) at low and intermediate mo-mentum Code: http://www.slac.stanford.edu/~schumm/lcdtrk.tar.gz

4. Idea: Noise vs. Shaping Time Agilent 0.5 mm CMOS process (qualified by GLAST) Min-i for 300mm Si is about 24,000 electrons

5. The Gossamer Tracker • Ideas: • Long ladders  substantially limit electronics readout and associated support • Thin inner detector layers • Exploit duty cycle  eliminate need for active cooling  Competitive with gaseous track- ing over full range of momenta Also: forward region…

6. TPC Material Burden

7. Pursuing the Long-Shaping Idea LOCAL GROUP • SCIPP/UCSC • Optimization of readout & sensors • Design & production of prototype ASIC • Development of prototype ladder; testing •  Supported by 2-year, $95K grant from DOE Advanced Detector R&D Program

8. SiLC: Silicon tracking For the Linear Collider PRC MeetingDESY, Hamburg, May 7 and 8, 2003 Aurore Savoy-Navarro, LPNHE-Universités de Paris 6&7/IN2P3-CNRS, France on behalf of the SiLC Collaboration SilC: an International R&D Collaboration to develop Si-tracking technologies for the LC

9. Helsinki Obninsk Karlsruhe Paris Prague Wien Geneve Torino Pisa Rome Barcelona Valencia The SiLC Collaboration Brookhaven Ann Arbor Wayne Santa Cruz USA Europe Korean Universities Seoul &Taegu Tokyo ASIA So far: 18 Institutes gathering over 90 people from Asia, Europe & USA Most of these teams are and/or have been collaborating.

10. Post-Doc Gavin Nesom (half-time LC postdoc from 1999 program) Student Christian Flacco (will do BaBar thesis) Faculty/Senior Alex Grillo Hartmut Sadrozinski Bruce Schumm Abe Seiden The SCIPP/UCSC Effort Engineer: Ned Spencer (on SCIPP base program)

11. SCIPP/UCSC Development Work Characterize GLAST `cut-out’ detectors (8 channels with pitch of ~200 m) for prototype ladder Detailed simulation of pulse development, electronics, and readout chain for optimization and to guide ASIC development (most of work so far)…

12. Pulse Development Simulation Long Shaping-Time Limit: strip sees signal if and only if hole is col- lected onto strip (no electrostatic coupling to neighboring strips) Charge Deposition:Landau distribution (SSSimSide; Gerry Lynch LBNL) in ~20 independent layers through thickness of device Geometry:Variable strip pitch, sensor thickness, orientation (2 dimen- sions) and track impact parameter

13. Uncorrelated Sampling Check

14. Carrier Diffusion Hole diffusion distribution given by Offest t0 reflects instantaneous expansion of hole cloud due to space-charge repulsion. Diffusion constant given by mh = hole mobility Reference: E. Belau et al., NIM 214, p253 (1983)

15. Other Considerations Lorentz Angle: 18 mrad per Tesla (holes) Detector Noise: From SPICE simulation, normalized to bench tests with GLAST electronics • Can Detector Operate with 167cm, 300 m thick Ladders? • Pushing signal-to-noise limits • Large B-field spreads charge between strips • But no ballistic deficit (infinite shaping time)

16. Result: S/N for 167cm Ladder At shaping time of 3ms; 0.5 mm process qualified by GLAST

17. Result: S/N for 132cm Ladder 132cm Ladder 300m Thick At shaping time of 3ms; 0.5 mm process qualified by GLAST

18. Not Yet Considered • Inter-Strip Capacitance (under study; typically ~5% pulse sharing between neighboring channels) • Leakage Current (small for low-radiation environment) • Threshold Variation (typically want some headroom for this!) But overall, 3 s operating point seems quite feasible  proceed to ASIC design!

19. Analog Readout Scheme: Time-Over Threshold (TOT) TOT given by difference between two solutions to TOT/t (RC-CR shaper) q/r Digitize with granularity t/ndig

20. 10 8 6 TOT/ 4 2 Why Time-Over-Threshold? With TOT analog readout: Live-time for 100x dynamic range is about 9 With  = 3 s, this leads to a live-time of about 30 s, and a duty cycle of about 1/250  Sufficient for power-cycling! 100 x min-i 1 10 100 1000 Signal/Threshold = (/r)-1

21. Single-Hit Resolution Design performance assumes 7m single-hit resolution. What can we really expect? • Implement nearest-neighbor clustering algorithm • Digitize time-over-threshold response (0.1* more than adequate to avoid degradation) • Explore use of second `readout threshold’ that is set lower than `triggering threshold’; major design implication

22. RMS RMS Gaussian Fit Gaussian Fit Resolution With and Without Second (Readout) Threshold Trigger Threshold 167cm Ladder 132cm Ladder Readout Threshold (Fraction of min-i)

23. Lifestyle Choices • Based on simulation results, ASIC design will incorporate: • 3 s shaping-time for preamplifier • Time-over-threshold analog treatment • Dual-discriminator architecture The design of this ASIC is now underway.

24. Energy (MeV) 0.1 1 10 But Can It Track Charged Particles? Photon Distributions at R = 25 cm See Upcoming Talks! z (cm)

25. Current Activity • ASIC architecture established with pulse sim… • ASIC design underway (chips in hand 1/1/04?) • Further pulse sim studies (x-talk, leakage current, angled tracks, etc. • Developing test stand (long ladder, readout, etc.)

26. Where Next? We’ve just begun the process of fleshing out the design of this `Gossamer Tracker’ In the 3-year R&D window, SCIPP needs to: • Design and submit prototype ASIC (chips in hand 1/1/04?) • Demonstrate ability to read out long ladders • Demonstrate resolution and dynamic range • Demonstrate passive cooling (data transmission is an issue!) • Mount testbeam effort to verify simulation studies, refine chip • Probably second submission and second round of testing