Course Tutor Dr R E Hurley

1. Semiconductor Device and Processing Technology Course Tutor Dr R E Hurley Northern Ireland Semiconductor Research Centre School of Electrical & Electronic Engineering The Queen’s University of Belfast

2. Semiconductor Device and Processing Technology 2. The future of silicon Moores Law What is realistic and possible for tomorrows production (advance to 22nm)? What next? New materials Blue skies and on into the future. Sheets of carbon atoms folded into a cylinder Unusual strength and electrical properties Promise to revolutionise electronics, computers, chemistry and materials science

3. International Technology Roadmap for Semiconductors http://www.itrs.net/

5. Proposed new technologies • Strained Si and SiGe • Improve high-k/metal gate further • Orientation (110 re 100) • Multi-gates • III-V or Ge • Metallic S/D

7. Current question today is how to advance to 22nm? (in production) IBM Research device

8. Current situation for immediate future Lithography (immersion, EUV) Mobility enhancement (strain eng) High-k/metal gates improvements Cu plugs contacts Porous low-k interconnects.

10. Lithography • 45 - 32 nm: Water immersion with ArF (NA = 1.35) • 45 - 32 nm: Double patterning technique • 22 - 13 nm: EUV expected • (critical parameters: feature resolution, line-edge roughness (LER) and exposure sensitivity. )

11. Researchers used double patterning with water-based immersion lithography to achieve a proof-of-concept 32 nm flash memory pattern. The final k1 was 0.19 after the split.

12. Strain techniques 32 – 45 nm: strain engineering for CMOS. Put the silicon lattice under strain improves mobility in channel. EpitaxialSiGe in source and drain Compressive stressed nitride over gate Strained SOI A buried SiGe island is very effective at inducing uniaxial tensile strain in the nFET channel for a 15% improvement in drive current. The TEM shows the device following silicon regrowth in the source/drain. (Source: IBM)

13. Ge layer on bulk SiSi layer on bulk Ge Si Ge Ge Si Ge on Si Si on Ge Ge contracts laterally expands vertically Si expands laterally contracts vertically

14. Strained silicon for high speed devices SiGe (X% Ge) Graded SiGe (0-X% Ge) Epitaxial Silicon Silicon wafer Strained Silicon

15. Relaxed silicon germanium layer by graded growth on silicon N.B. diagram exaggerated. Lattice mismatch is only 4.2%! With CVD, production of layers is relatively easy. At QUB we have experimented up to 60 layers. relaxed Si1-xGex step step Si

16. Strained silicon growth onto silicon germanium Strained silicon for novel band gap engineered n- and p- MOSFETswith significantly improved performance compared to pure silicon.

17. TEM image of graded SiGe buffer layer Cross-sectional TEM image of a virtual substrate grown at 800 °C by ultra-high-vacuum CVD, showing the compositionally graded buffer Si1−xGex layer (x from 0 to 0.25) with significant number of dislocations and the constant-composition Si0.75Ge0.25 buffer free from dislocations [Churchill et al., 1997].

18. n+ n+ Strained silicon MOST

19. Intel Approach to Strained Silicon Silicon in channel under compressive stress P MOST 25-50% Silicon in channel under tensile stress n MOST 10%

20. Low-k for interconnects At 22nm The interline capacitance between conductor lines (interconnects) must be reduced. Use low-k (2.2 to 2.5)

21. Threshold voltage, Vt ,variability problem in MOSFETs • As size reduces statistical variations in Vt start to show • Random dopant fluctuations are major cause • For long transistors Vt = VFB + 2ΦF - Qd/Cox • [ VFB == flat band voltage, ΦFis Fermi potential, Qd = depletion charge and Cox = MOS structure capacitance.]

22. Threshold voltage, Vt ,variability problem in MOSFETs The Vt fluctuations due to the random variations of dopant in the channel are given by i.e. ΔVtis a function of area and dielectric thickness But this model does not work when dimensions are very small

23. Short channel effect • Space-charge at source/drain junctions is around 0.05 µm for 0.18 and 0.12µm CMOS. • When CMOS CD < 0.12µm , space-charge affects channel length significantly and potential barrier is reduced and Vt is reduced. • This effect can vary from one transistor to the next.

24. Threshold voltage, Vt ,variability problem in MOSFETs • High-k reduced ΔVt, but further improvements needed: • Control work-function in the TiN gate • nFET – Thin lanthanum oxide layer cap on high-k • pFET - Thin aluminium oxide layer on high-k

25. Copper interconnects into memory devices Flash memory uses high fields needing thicker barrier layers and denser oxides The interconnect of a flash device shows on-pitch Metal 1 with high-aspect-ratio vias above, which press the capabilities of barrier/seed coverage and copper fill. (Source: Micron)

26. Copper for contacts • 32 nm: Copper to replace tungsten plugs • (plugs make contact to S/D). Contact resistance affects RC and power consumption. • Issues are barrier layers to protect silicon. (Cu poisons Si!). Barrier must be thin but reliable!

27. Beyond 22nm and high risk research Possible and realistic but difficult • Multi-gate devices (MuGFETs) • Ge and III-V • System on chip and 3D fusion technology.

28. MuGFET Benefits from reproducible threshold voltage and low OFF leakage, but difficult to implement in production

29. ITRS New material needs • Looking beyond 2010, for CMOS new materials required: • For channel: SiGe, Ge or III-V • In combination with high k dielectric and metal gates (to replace polysilicon) √

30. Germanium, early days. • Historically first bipolars and ICs were made from Ge • Si replaced Ge because of SiO2 properties • GeO is unstable at 4000C being volatile Bardeen, Brattain, Shockley, 1947. Nobel Prize, 1956

31. Importance of germanium in todays technology • Genow reconsidered for: • Extending scaling limits of CMOS technology (<45nm) • Near IR optical telecommunication devices • Solar energy

32. Semiconductor Properties - Ge, Si, GaAs compared.

33. Germanium significant properties • Electron mobility 3900 cm2/Vs (Si 1500) • Hole mobility 1900 cm2/Vs (Si 450) • Band gap 0.66 eV (Si 1.1 eV)

34. Advantages of Germanium • Ge provides high electron and hole carrier mobility -- faster CMOS, larger drive currents. • Compatibility with high k dielectric and low temperature metal gate technology • Ge lattice match to GaAs permitting epitaxial growth -- n channel MOSFET • Integration of rf & quantum electronics -- integration of opto-electronics (smaller optical band-gap)

35. Germanium Highest hole mobility High electron mobility Low energy band gap High density More fragile than silicon Scarce, expensive Suitable for GaAs epitaxy Applications High performance CMOS Low temperature operation IR detection/imaging High energy particle detection Integrated optics & electronics Solar cells

36. Germanium problems with MOST • Unstable oxide. GeO2 forms volatile GeO at 4000C, hence poor passivation of Ge surface • Dopant solubility (in electrical terms) is poorer than expected. (Clustering? Vacancy-acceptor centres?) • Dopant loss during annealing (related to ion-implantation damage) • Some success with B, but n dopants ( implant damage greater) require higher anneal temps. Leads to high-k crystallisation, Ge diffusion etc..

37. Germanium: More problems! • Smaller band-gap (than Si) leads to high intrinsic (ni),carrier concentration leading to surface leakage in p-n diode periphery. (problems also with surface states) [Satta, 2006} • Lattice mismatch with silicon substrate means grading layers of SiGe or ‘smart-cut’ type solution if it can be made to work. Thermal expansion coefficients are significantly different.

38. GeMOSFET schematic GeMOSFET: p-n junction and metal gate/dielectric stack Houssa et al., from Germanium-Based Technologies, Elsevier Ltd. 2007. Volume and surface charge carriers must be considered

39. Ge gate-stack issues Thin epi-Si oxidised, with HfO2 by ALD give C-V improvement over GeON interlayer Houssa et al., 2007

40. GeMOSFET– circular geometry Self-aligned, surface channel p-GeMOSFET ZrO2 (EOT 6-10 A), Pt gate. BF235keV implant, 400C max temp in entire process. Chi On Chui, Stanford University

41. TEM showing interface problems • HfO and ZrOdirect onto Ge leave a 3A GeO layer- enough to create instabilities and irreproducible characteristics Ge/GEO2/HfO2 gate stack (Houssaet al., 2007) High density interface states, high leakage.

42. Shallow junctions: ion implantation problems • Channelling is significant • End of range straggle • Annealing to remove damage and activation leads to loss of dopant. • Annealing temp must be kept below 400 to 500C to prevent: • Crystallisation of high-k material. • Out-diffusion of dopants. • Degradation of interfaces.

43. Can GeOI really be used for CMOS? • Good p-channel devices OK • n-channel mobility is poor • Therefore, Ge for p-MOS • GaAs or strained Si for n-MOS • GaAs can be grown by epitaxy on Ge

44. Germanium on Insulator (GeOI) • Other possibilities for GeO • Enhanced performance devices • High speed photodetectors • Template for GaAsepitaxy (→Si/III-V integration)

45. Smart-Cut method for GOI (QUB)

47. 3D integration → fusion technology FUSION = integration of memory, logic, sensor, processor and software using 3D stacked ICs SEM of a 3-D via chain with 10,000 vias/mm2 density after etching the silicon in the top die. (Source: IMEC)

48. Optoelectronics: Photons weigh 250,000 times less than electrons, so why notuse them to carry data? Bringing optical technology down to the processor level, DNA: ?? Immersion lithography: This technique entails putting wafer in water and shooting the picture! Imprint lithography: A stamp (by e-beam litho) is immersed in liquid to create a pattern. HP. EUV lithography: By using highly polished mirrors and a laser EUV machines can create lines a few nanometers in length. Intel, AMD and IBM are the big proponents. 2009? (Think not! “SemiconInt”)

49. Spintronics: Uses the magnetic field created by an electron's spin (rather than the transport of electrons). • Phase change: memory technology that relies on heating, and reheating, CD-like material. Philips and Intel, • Nanowires and nanotubes: transport electrons from one point to another to create a 1 or 0. how to put billions into arrays.? • Crossbar latches: This is one of the more radical transistor makeovers, HP. bad circuits no statistical consequence • Resistance switching: Resistance change of molecule. • III-V compounds: These materials behave like silicon but are faster. They also cost a lot more.