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Course Tutor Dr R E Hurley

Semiconductor Device and Processing Technology. Course Tutor Dr R E Hurley. Northern Ireland Semiconductor Research Centre School of Electrical & Electronic Engineering The Queen’s University of Belfast. Semiconductor Device and Processing Technology.

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Course Tutor Dr R E Hurley

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  1. Semiconductor Device and Processing Technology Course Tutor Dr R E Hurley Northern Ireland Semiconductor Research Centre School of Electrical & Electronic Engineering The Queen’s University of Belfast

  2. Semiconductor Device and Processing Technology 1. Introduction – course content for Cartagena NISRC, Belfast Historical overview of semiconductor industry

  3. Course Content • 1. Introduction and historical overview of semiconductor industry. • 2. Silicon - properties and preparation. • 3. Devices I - Fundamentals and basic types. • 4. Devices II – Processing and photolithography • 5. Equipment – Industry and the research Fab Lab • 6. The vacuum environment for semiconductor processing. • 6a. Special processes I. Evaporation and sputtering • 7. Special processes II. Ion implantation • 8. Recent years and new developments I. SOI • 9. Recent years and new developments II. The future of Silicon • 10.Recent years and new developments III. Beyond silicon

  4. AN IRTU DESIGNATED CENTRE OF EXCELLENCE ESTABLISHED IN 1991 WITH £3.5M FUNDING FROM THE EU STRIDE PROGRAMME ( University Silicon Laboratory 1966 ) N I SEMICONDUCTOR RESEARCH CENTRE • A versatile research laboratory • Research on niche areas of silicon technology & devices • Thin films facility

  5. Entry/Exit to NISRC cleanroom

  6. NORTHERN IRELAND SEMICONDUCTOR RESEARCH CENTRE • 4 inch - 8 inch wafer capability (100-200mm) • 1 micron CMOS capability NISRC Function and Ethos • Collaborative Research • Training • Start up companies • Sub-contract work • Inward investment

  7. Academic Staff Director : Professor Harold S Gamble Dr B Mervyn Armstrong (Reader) Professor G Alastair Armstrong Dr S J Neil Mitchell (S L) Dr David W McNeill ( L )

  8. NISRC Staff • 5 Academic staff • 14 Research Engineers • 6 PhD students • 2 Technicians Annual Income for research > £0.6M

  9. INDUSTRIAL CONTACTS • Andor Technologies •Astrium • Seagate Technology •Randox LaboratoriesNational Semiconductor• XFAB • Astrium •BAe • R.A.L. Oxford • Hewlett Packard • Oxford Instruments •Celestica Ltd, Stoke • IceMOS Technology Ltd •Intel Ireland • Zarlink

  10. COLLABORATION WITH UNIVERSITIES • AGH - UST, Krakow, and IET, Warsaw, Poland • UniversitaInsubria, Como, INFNFerrara, Italy • Southampton, Surrey, Imperial, Liverpool, Waterloo Canada • Trinity College, Dublin • Leeds, Cambridge, Sheffield, Imperial • Liverpool, Edinburgh, • Louvain la Neuve, Belgium • University of Ulster ------------Nanotec NI • Queen’s University Physics, High Frequency Electronics

  11. University Contacts and Networks UK Network: Silicon Research and Exploitation For the Nanotechnology Era National Microelectronics Institute Power Electronics Network EUROSOI Network of Excellence METAMORPHOSE Network of Excellence (MetaMaterialsorganized for radio, millimeter wave, and photonic superlatticeengineering)

  12. CURRENT RESEARCH AREAS • Silicon on Insulator [SOI] technology • Strained Layers on Insulator • Atomic Layer Deposition of high-K dielectric • High Energy particle detection • CCDs • MicroElectroMechanical Systems • RF MEMS and MMICs • Frequency Selective Surfaces • CVD of metal magnetic layers

  13. Chemical Vapour Deposition APCVD Silicon dioxide LPCVD Silicon nitride LPCVD tungsten disilicideTEOS Silicon dioxide tungsten, copper, iron cobalt PECVD Silicon nitride Silicon dioxide LPCVDPolysilicon Epitaxial silicon EpitaxialSiGe

  14. Photolithography and Etch GCA wafer track EVG double sided aligner 2.0m GCA g-line stepper 1.5m SEM EBL 0.1m SU-8 Polyimide BCB Reactive Ion Etching STS Deep Reactive Etching Alcatel*

  15. Other Processes Precision Grinding Wafer Polishing Ion implantation As,B,P,He,H,N Porous silicon Damascene copper Thick film PZT Atomic Layer Deposition* HfO2 WN

  16. Analysis +Measurement SEM I-Vs Alpha step C-Vs Nanospec C-Ts FTIR 4 Pt probe SAM ADE IRCCD Particle counter AFM Probers FIB Microscopes TEM

  17. A summary of the history of Microelectronics with some illustrations, beginning with early electronics

  18. Milestones in electronics history • 1883 Edison. Current flowed from hot filament to anode across vacuum = Edison Effect. • 1904 Fleming makes diode based on above. Rectifies and and detects radio waves. • 1906 Lee de Forest adds grid = triode → amplifiers and oscillators. • 1900 Solids rectify! (CuO, Si, PbS) → solid state electronics. • 1926 MESFET proposed (Lilienfeld);1928 MOSFET

  19. Milestones in electronics history • 1940 pn junction produces 0.5 V on exposure to light. (Ohl, Bell Labs) • 1945 Group established to develop replacement for vacuum tube (valve). (Bell Labs. Led by Shockley) • 1947 Point Contact Transistor invented (Bardeen, Brattain and Shockley)

  20. The First Transistor A slab of Ge/Sn alloy with closely-spaced point gold contacts → The first working solid-state amplifier using germanium. • 1949 Teal labours through the night in the Bell Labs (no extra pay?) to develop seed-pulling in hydrogen to produce pure germanium crystals. • Shockley is vindicated over the question of minority carrier injection. Bardeen, Brattain, Shockley, 1947. Nobel Prize, 1956

  21. http://semiconductormuseum.com/ • 1948 First developmental transistor. • 1949 3700 units produced. • Transistor Size (7/16”OD X 1/2”H) Cardboard Package with Serial Number and Device Characteristics. • Ic = 3mA, Ie = 1.5 mA

  22. 1951 First junction transistor. In alloyed to Ge, (Shockley, Sparks and Teal) • 1952 Teal moves to Texas and pioneers pure silicon using • crystal-pulling technique. • 1954 First silicon transistor cut from bar of pure silicon (Texas) • 1954 Oxide masking process = oxidation, photomask, etch, diffuse. (Bell) • 1954 First transistor radio. The Regency TR1 using 4 Texas Ge transistors. The Rock’n Roll era! Independent from parent’s radio!! • 1955 First field-effect transistor (Bell)

  23. TYPE Bead Type Germanium Point Contact USAGE Early Prototype Transistor DATE INTRODUCED 1951 CASE STYLES • Plastic BeadAVAILABILITY Very Rare (Prototype) • Transistor Size (1/8” Diameter Bead)

  24. First diffused base transistors. Developed at Bell Labs in 1954 (germanium) and 1955 (silicon). Major breakthrough for future semiconductor technology (ICs and high frequency transistors). Transistor Size (1/2”Diameter X 1/2”H) TYPE Germanium/Silicon Diffused Base USAGE First Developmental Diffused Transistor DATE INTRODUCED 1954/55 CASE STYLES Clear Plastic Dome

  25. First silicon in commercial use.

  26. 1958 IC invented. (Bell Labs). Jack Kilby makes oscillator with five components connected with Au wires. Awarded Nobel Prize with 2 others in 2000! • 1959 Planar Technology invented. (Fairchild, Sprague) • Pn junctions in Si covered in oxide, etched through Al then etched to form conductors to other parts of circuit.

  27. 1958 Sold for Car radios (yes, in America!) and power supply switching circuits. • Only $3.75 in 1958!!

  28. 1960+ IC Milestones • 1960 Epitaxial Deposition invented (Bell) (single crystal layer is deposited on crystal substrate) • 1960. MOSFET (Kahng and Atalla, Bell Labs) • 1960 0.524 inch (13.335 mm) silicon wafers • 1961 First commercial ICs (Fairchild, Texas) • 1962 TTL invented • 1962 Semicon. Industry exceeds 1$ billion in sales • 1963 First MOS IC (pMOS) (RCA) • 1963 CMOS invented (Wanlass, Fairchild) [Stand-by power drops by 106! compared to bipolar].

  29. 1960+ IC Milestones • 1964 Commercial contact printer (into 1970s…) • 1965 Moores Law proposed (Gordon Moore).[Components per IC doubles every 18 months. Idea is to satisfy minimum component cost.] • 1966 Self-aligned gate MOSFET (Bower and Dill). [The gate = source/drain mask]. • 1966 Single transistor DRAM cell invented. (IBM) [1 bit stored by C charging using 1 FET. • 1967 NMOS • 1968 64 bit bipolar array chip • 1969 BiCMOS

  30. Gordon Moore’s original graph, 1965 Moores Law Gordon Moore Director of R & D at Fairchild

  31. 1970+ IC Milestones • 1970 2.25 inch Si wafers. • 1970 1st commercial DRAM metal gate NMOS. 1kbit [memory cell = 200 µm2, die 10 mm2 at $21 each. • 1971 Microprocessor invented. 108 kHz clock, 4- bit, 4004, 2300 transistors. PMOS 10µm line-width, die 13.5 mm2. • 1972 8 bit, 8008 • 1972 Scaling laws invented. [keep electrostatic field constant and performance improves! Leads to end of bipolar supremacy in the 90s] • 1974 8080 1st commercially successful (Altair comp.) microprocessor. 6µm, 6000 transistors. 200kHz.

  32. 8008 (1st home computer 1972) 15.2mm2 • 8080 1974 • Used in Altair computer 20.0mm2

  33. 1970+ IC Milestones • 1973 Projection printing (revolutionary). • 1973 3 inch Si wafers • 1975 100 mm Si wafers • 1976 16 kbit DRAM 5µ features. $33 • 1978 8086/8088. 5-10 MHz 8088 selected for IBM PC. • 1978 Step and repeat camera (GCA). • 1978 industry passes $10 billion • 1979 64 kbit DRAM 3µ features. $47 • 1979 125 mm Si wafers 31 mm2

  34. 1980+ IC Milestones • 1981 150mm Si wafers • 1981 256 kbit DRAM 2µ features, 45mm2 die, $51 • 1982 Intel 80286. Si gate/CMOS. 1.5µ linewidth *. • 1983 16 kbit EEPROM (floating gate, NMOS, 2 transistors per cell). • 1984 Flash memory invented (Flash = flash erase in blocks. 1 transistor per cell) (Masuoka, Toshiba) • 1985 Commercial flash. 256 kbit chip (Toshiba) • 1985 Intel 80386DX (32 bit processor) • 1985 200 mm Si wafers • 1988 4 Mbit DRAM 0.8µ. 95 mm2 $124. • * 80286. 134,000 transistors, 6-12Mhz, 68.7 mm2

  35. 1990+ IC Milestones • 1991 16 Mbit DRAM 0.5µ CMOS. 3-4 polylayers, 2 metal layers.130 mm2 $275 • 1993 Intel Pentium. The first processor for > 1 instruction per clock cycle. • Si gate biCMOS 0.8µ. • 3 million transistors. • 1994 $1 billion industry • 275 mm2

  36. 1990+ IC Milestones • 1997 Pentium II. Si gate CMOS. 0.35µ 7.5 million transistors. 300 MHz clock. 209 mm2 die. • 1998 256 Mbit DRAM. CMOS. 0.25µ First use of high k dielectrics. $575. • 1999 Pentium III. Si gate CMOS 0.18µ 28 million transistors. 700 MHz clock. 140 mm2 die.

  37. 2000 Pentium IV. Si gate CMOS 0.18µ 42 million transistors. 1500 MHz clock 224 mm2 die. • 2001 Pentium IV. 130nm. PolySi CMOS 6 copper layers. 55 million trans. 146 mm2 die. • 2003 Pentium IV. 90 nm. 125 million transistors. 112 mm2 die. • Strained Si using SiGe + stress layers. • 2005 Pentium IV. 65 nm.8 Cu layers 169 million transistors. 190 mm2 die. • 2007 Intel Core 2 Duo 45 nm. First high-k gate oxide in production. Dual metal gates. 9 Cu layers. 410 million transistors. 106 mm2 die.

  38. Moores Law for Intel CPU’s • Is it rolling over?

  39. Intel’s proud predictions for years ahead. • A worldwide silicon fab network with seven high volume fabs and another due to open in 2008 • The world's first 32nm silicon technology on-target for delivery in 2009 • The world's first 2-billion transistor microprocessor delivered in next-generation Intel® Itanium® processors codenamed Tukwila • Hafnium-based high-k metal gate in production today • Advanced research into tri-gate transistors and silicon nanotechnology

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