Course Tutor Dr R E Hurley

1. Semiconductor Device and Processing Technology Course Tutor Dr R E Hurley Northern Ireland Semiconductor Research Centre School of Electrical & Electronic Engineering The Queen’s University of Belfast

2. Semiconductor Device and Processing Technology 2. The future of silicon Life left in silicon? New materials

3. Silicon advantages • Silicon is strong and cheap. (III-V and Ge expensive). • Si bonds cleanly to oxide. (Passivation (H) techniques exist for dangling bonds (free electrons). • Can make large ultra-flat wafers. • Silicon can still be used with new dielectrics (HfO2) and gate materials.

4. Advantages of silicon oxide • Grown by simple exposure to oxygen gas or water vapor at elevated temperatures, (until recently remained the gate insulator of choice). • Success based on the wonderful properties of the silicon/silicon dioxide interface. (This interface has only about 1012 cm−2 electrically active defects). • After a simple passivating hydrogen exposure, 1010 cm−2 defects remain—only one defect for every 100,000 interface atoms!

5. Scaling of the SiO2 gate oxide over tech. generations ½ pitch DRAM

6. At 10Å tunnelling current densities reach > 100 A/cm2 ! • 45 nm is the point where problems arise and this is being reached now. • SiO2 has become too thin to prevent leakage (→ heat dissipation problems, breakdown)

7. High resolution TEM by INTEL TEM of 12Å SiO2 gate oxide at the 90nm logic technology

8. High resolution TEM by INTEL TEM of SiO2 at 8Å gate width

9. 15 nm Si transistors with 0.8 nm SiO2 gates Inversion split CV measurements Experimental NMOS

10. Leakage measurements at 8Å gate width Inversion gate leakage current density v. volts, Vg

11. When SiO2 gets very thin SiO2 creates big heat dissipation problems. SiO2 has run out of atoms! Find a new dielectric with high k

12. Scaling with high k dielectric • Direct tunnelling causes leakage • For the same capacitance, C = ε0 κA/t • t can be increased for higher κ • This eliminates tunnelling • To compare with silicon, the equivalent oxide thickness (EOT) is defined as: • EOT = (3.9/κ)t(highk)

13. Gate leakage for high-k dielectric compared to SiO2 Accumulation gate leakage for high-k/metal gates and SiO2/ polySi gates

14. Some possible high-k materials

15. High-k candidates summary

16. MOCVD system for HfO2 Vapours introduced react with heat on surface

18. Deposition by Atomic Layer Deposition , ALD • A two stage process with cleaning and purging cycles • Clean surface • Admit a pulse of H2O (forms OH groups) • Purge with nitrogen and pump • Admit a pulse of metal precursor, Mxy ( e.g. HfCl4) (react with OH to leave metal on surface)

20. e.g. A(s) = oxygen, B(s) = Hf

21. Schematic of deposition process Precursor Cl H2O Oxygen Metal

23. QUB System

24. QUB System

26. Inside the QUB system

27. Problem areas with high-k dielectrics • Gates were traditionally polysilicon • High k and polysilicon gate causes problems: • surface defects affect Fermi level at interface →high unpredictable Vt. • Optical phonon interactions (polarizable dielectric →reduced mobility in channel) • Metal gates can solve these problems.

30. INTEL transistor characteristics Si/highk/metal gate Saturation drain current is good

31. Way forward with silicon Create quality interface to dielectric Grow new type of dielectric (High k) Re-engineer transistor to make it work Solve production problems and build

33. Silicon transistor at 22 nm using silicon (INTEL)

34. BICMOS