Course Tutor Dr R E Hurley

1. Semiconductor Device and Processing Technology Course Tutor Dr R E Hurley Northern Ireland Semiconductor Research Centre School of Electrical & Electronic Engineering The Queen’s University of Belfast

2. Semiconductor Device and Processing Technology 2. Silicon – properties and preparation

3. Atomic no. 14. All levels filled to 3p. • 3p has 2 electrons in levels with capacity 6. • Hence Si shares with 4 nearest neighbours to satisfy unfilled 3p energy levels.

4. Silicon physical properties in the solid state • Si is atomic number 14 and shares its outer electrons with the 4 nearest neighbour atoms forming covalent bonds

6. The diamond (C, Si, Ge) unit cell • Bond to nearest neighbours • All atoms in crystal are bonded and form one giant molecule!

7. s2p2 electrons → sp3 → shared electron pairs → crystal formation • s2p2 electrons → sp3 → shared electron pairs → crystal formation Hybridization (the electron clouds repel each other)

8. Silicon unit cell facts • Lattice constant, a = 0.543 nm • Unit cell has 8 atoms • 1 atom corner, 3 atoms face, 4 atoms at ¼, ¼, ¼ lattice points • Unit cell volume is 1.6 × 10-22 cm3 • 6.25 × 1021 unit cells/ cm3 = 5 × 1022 atoms/cm3 • Nearest neighbour distance in 0.235 nm • Covalent radius is 0.118 nm → 27% packing ratio

9. Silicon crystal for integrated circuits (ICs) • (111) is the cheapest. Used for bipolars • (110) is difficult to produce (experimental) • (100) have best surface properties and used for MOST ICs.

10. Effect of (100), (110), (100) on surface properties • (100) – 4 dangling surface bonds per unit cell • (110) - 8 dangling (+parallel) bonds per unit cell • (111) - 4 surface bonds per unit cell

13. Band structure of semiconductor • Allowed energy levels of 1 atom overlap and form bands when atoms form solid • The outer 2 levels → valence and conduction band • At 0 degrees Kelvin, conduction band is empty, • valence band is full. • Forbidden energy gap exists

14. Silicon band structure at 3000K

15. Silicon band structure • Semiconductors. Eg = 0.1 - 2.0 eV • Insulators. Eg = several eV • Conductors. Overlapping valence and conduction bands • For silicon, Eg (T) is given by • T is in 0K and 1.17 = Eg for Si at 0 0K.

16. Silicon energy gap v. Temperature

17. Intrinsic conductivity Holes and electrons

18. Intrinsic conductivity • Electrons excited by thermal energy jump to conduction band and become mobile intrinsic carriers with density, ni : k is Boltzmann’s constant

19. Si intrinsic carrier concentration v. temperature

20. Doping silicon • Group III → excess +ve carriers = holes = p-type • Group V → excess –ve carriers = electrons = n-type • (Excess = excess of intrinsic concentration) • Carriers can be majority or minority

22. Ionisation energies of dopants in silicon

23. Law of Mass Action • In equilibrium: • Majority carrier density x Minority carrier density = constant for material and temperature • i.e. nh x ne= constant = ni2 • ni = 1.4 x 1010 cm3 for silicon • Why? • Generation rate is constant, f(T) • Recombination rate is f(nh x ne, T)

24. Mobility • Average velocity of carriers = carrier drift velocity, vd = E, where µ is the mobility = qτ/m*, E is the field. • (τ is meant time between scattering collisions, m* is effective mass) • This is not valid at very high fields when scattering processes are non-uniform

25. Mobility v. doping concentration • 1019 • 1014

26. Resistivity Standard well-known formula For a doped semiconductor, n is carrier concentration

27. Resistivity of silicon v. impurity concentration at 300K. • 105 • 10-3 • 1011 • 1021

28. The Fermi Level for Silicon • The position of the Fermi level relative to the top of the valence band for intrinsic silicon is: Mdh = 1.9117, mdc = 0.3268, Mc = number of equivalent minima in conduction band. (Approximately at the centre of energy gap)

29. Fermi Level for extrinsic silicon n or p >> ni, Eiis the Fermi level for intrinsic silicon

30. Fermi level v. temperature and doping

31. Defects in crystals • In a crystal point defect concentration depends on thermal fluctuations and vapour pressure • In silicon only thermal fluctuations important • Defects will affect electronic properties • Defect concentration depends on energy of formation and equilibrium temperature. • Processes can produce defects and affect performance

32. Vacancy defects in silicon

33. Ways to form defects in silicon • In silicon unit cell there are 5 interstitial positions • (½, ½, ½,),(¼, ¼, ¼),(¼,¾, ¼), and (¾, ¾, ¼) • 3 ways to make point defects: • Schottky defect – silicon atom jumps to interstitial position and diffuses to surface, leaving vacancy. • Frenkel defect – silicon atom jumps to an interstitial, creating vacancy/interstitial pair. • Surface generation – surface atoms move to interstitial sites within lattice.

34. surface

35. No. of Frenkel defects per unit volume

36. Energy to form Schottky defect = energy to remove an atom from lattice and out of crystal = 2.3 eV. Using statistics and basic thermodynamics can be shown that no. of defects, Cs is given by: (N = atoms/cm3)

37. Defects can be charged • Vacancies or interstitials can capture or release an electron: • Energy levels for + and – ve charged vacancies exist at 0.35 and -0.57eV in silicon energy gap, but double_charged –ves can also exist.

38. Interstitial defects in silicon

39. Effect of silicon processing • Processes causing defects: • Thermal oxidation • Thermal nitriding • Ion implantation • Exposure to radiation

40. Extended defects • Silicon processing may produce extended defects: • Dislocations • Twinning • Stacking faults

41. Dislocations in silicon • Strain, a distortion of the crystal lattice is produced by stress. Sources of stress are: • Mechanical forces (high temperatures • High dopant levels (dopants with size mismatch to silicon) • Thermal gradients: • Thermal gradient strain, S = α Y ΔT • α = coefficient of expansion, Y = Youngs Modulus, ΔT is temperature difference between centre and edge of wafer. • If Stress > yield strength of silicon → dislocation

42. Formation of edge dislocation

43. Twinning (2 regions at differing orientations.) Usually means many dislocations, micro-twinning can be produced by ion implantation

44. Stacking faults (oxidation, implantation, epitaxy) Excess atoms in one region

45. Production of electronic grade polysilicon from SiO2 The process starts with sand from Australian beaches Arc furnace with coal or wood reduces SiO2 making 98% pure solid silicon. Si powdered with HCl in fluid bed to form SiHCl3 .

46. Making silicon Then distilled to high purity. Reduced with high purity hydrogen to yield high purity silicon.. This is one large polycrystal

47. Impurities in silicon

48. Making high purity silicon • Czochralski technique: • Small seed crystal dipped into molten Si bath and slowly withdrawn. • The bath and growing “boule” are rotated in opposite directions. • Argon atmosphere, impurities may be added for doping.

49. Czochralski crystal puller

50. Summary of wafer making processes • Pull crystal under argon, rotating. Forms ingot. • Grind ingot to fixed diameter. • Saw off ends of ingot (waste) • Saw into wafers (0.5 to 0.8 mm thick) • Edge grind to remove sharp edges • Lap wafers to flatten and ensure faces are parallel • Wet etch to remove damage from lapping • Polish to mirror finish • Final clean (removes contamination)