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PIDS Update July 13, 2011 San Francisco, CA, U.S.A.

PIDS Update July 13, 2011 San Francisco, CA, U.S.A. Speaker: Kwok Ng (PIDS U.S. Chair). PIDS Roster. C=Chair, CC=Co-Chair, VC=Vice-Chair. Outline PIDS Mission and Technical Sub-Groups Logic Memory Reliability 2011 Edition Update Summary Plans for 2012 Edition.

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PIDS Update July 13, 2011 San Francisco, CA, U.S.A.

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  1. PIDS UpdateJuly 13, 2011San Francisco, CA, U.S.A. Speaker: Kwok Ng (PIDS U.S. Chair)

  2. PIDS Roster C=Chair, CC=Co-Chair, VC=Vice-Chair

  3. Outline • PIDS Mission and Technical Sub-Groups • Logic • Memory • Reliability • 2011 Edition Update Summary • Plans for 2012 Edition

  4. PIDS = Process Integration, Devices, & Structures • Mission: • Provide physical and electrical requirements and solutions for sustaining IC scaling in digital logic technologies and memory technologies. • Scopes: • Performance (speed, density, power, functionality…) • Structures • Process-integration challenges • Reliability

  5. PIDS Technical Sub-Groups • Logic (Leads = C. Cheung, K. Ng, H. Wakabayashi) • HP = High Performance (e.g., mP…) • LOP = Low Operating (Dynamic) Power (e.g., notebook…) • LSTP = Low Standby (Static) Power (e.g., cellular…) • Memory: DRAM (Lead = H. Inoue)Nonvolatile (Leads = R. Liu, H. Inoue) • Reliability (Leads = C. Cheung, J. Park)

  6. 2011 Update: Logic • CV/I slope of 13%/year maintained. (See plan for next year.) • After series of workshops followed by survey (with other TWGs ERD/ERM/FEP), add III-V (for n-channel) and Ge (for p-channel) as alternate channel materials for HP (high-performance) at low-power.Product introduction year = 2018. • Add dynamic power metric CV 2 on all logic options.Only as monitor, not as specs.

  7. 2011 Update: DRAM • Updates were mostly based on survey performed by Japan PIDS, complete in March 2011. • Half-pitch unchanged (compared to 2010 version) for near years. Minor changes for far years (slightly relaxed). • Cell size factor transition from 6F2 to 4F2 unchanged (2013). • Unchanged,Vertical Channel transistor will be launched in 2013, in place of Recessed Channel, and continues till end of roadmap.

  8. 2011 Update: Nonvolatile Memory NAND flash survey had been performed by Japan PIDS (completed March 2011). Together with market observations, following changes had been made: • Compared to 2010 Edition, half-pitch scaling is accelerated by 1 year. • Product density (in Gb) is accelerated by 1 year. • Introduction of 3-D NAND is delayed by 1 year to 2016. • Unchanged: Transition from 3 to 4 bit/cell is projected in 2019. • New 3-D table format:Distinguish 3-D NAND from planar NAND with separate values in half-pitch, MLC, density... • Other NVM devices (NOR, MRAM, STT-MRAM, PCRAM) updated.STT-MRAM merged into same table.

  9. 2011 Update: Reliability • Introduce a new category for highly reliable system (e.g., medical) with more stringent early failure rate that improves by 15% year-over-year.

  10. Plans for 2012 Edition • Continue to discuss with other TWGs to consider merging low-power technologies LOP and LSTP. • Multi-gate (FinFET) structure is being considered to pull in from 2015. • To address lower power requirement, with the trend that chip clock frequency increases per year has slowed down, transistor speed CV/I slope will be decreased from 13%/yr to 8%/yr.Consequences: Lower Vdd and most likely relaxed gate length. • Working closely with Modeling TWG to compare currently obtained MASTAR results with TCAD.

  11. Plans for 2012 Edition (cont’d) • New DRAM survey will be completed by end of January 2012. Additional survey items based on latest process technology (i.e., buried WL, cell FET materials, etc.) will be added. • New NAND survey will be conducted. • (End)

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