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Status of measurements of FE-I4 SEU and PRD

Status of measurements of FE-I4 SEU and PRD. A.Rozanov 30 .05.2011. Hardware problems. Found that most of the coherent SEU were due to big Vdda drop in the 3.5m grey flat cable (1 om )

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Status of measurements of FE-I4 SEU and PRD

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  1. Status of measurements of FE-I4 SEU and PRD A.Rozanov30.05.2011

  2. Hardware problems • Found that most of the coherent SEU were due to big Vdda drop in the 3.5m grey flat cable (1 om) • Temporary solution: reduce at maximum Idda by switching OFF amplifiers and discriminators: Amp*=0, PrmpAmp*=0, DisVbn*=0. After that Idda2=55-100 mA, so voltage drop only 55mV-100 mV. • Two thick cables with Mollex connectors produced • Thanks to Ruud for sendingExtension Board to CERN • Patrick Breugnon will test the setup with IOboard+extension_board+Mollex cable to be ready for installation if needed • MD Wednesday 25.05.11 was canceled, we decided to postpone the access, as no urgent need now • Improve voltage regulator performance by cold start (unplug USB, OFF Vddd, OFF Vdda) at the start of each run. No more problems with low set Vdda • Cold starts seems to improve running stability of STControl, can go up to 500 iterations

  3. Preliminary SEU results chips# 27 and 28 • No more coherent SEU (or very rare) • Good matching first and second readout (with very rare exceptions) • Runs 50,51,52,53,54 • Type A (old) DC29 TDAC[1] and FDAC[1] • Type B (new) DC30 TDAC[1] and FDAC[1] • Normal SEU (<40 errors/bunch) • Coherent SEU(>40 errors/bunch )

  4. Measurement of beam profile by SEU • Chip 27, 28 run 52, Vdda2=1.5V-0.1V

  5. Normal SEU chip #27, run 52, Vdda=1.5V-0.1V

  6. Normal SEU chip 28, run 52, Vdda=1.5V-0.1V SEU same as in thechip #27, almost not visible in type B (new) latches

  7. Coherent SEU chip 27, run 52 1 coherent in old latches, 0 coherent in new latches for 300 iterations (rate ~0.3%)

  8. Very preliminary SEU results chips# 27,28 • Normal SEU per spill ~20 10 10protons/cm2 • Vdda1= 1.5V – 0.1V(drop) • Chip 27 Type A 2.8 seu/spill/672bits (last week 4.6) • Chip 27 Type B 0.1 seu/spill/672bits • Chip 28 Type A 3.0 seu/spill/672bits (last week 8.0) • Chip 28 Type B 0.1 seu/spill/672bits • Coherent SEU • more often inA • Chip 27,28 ~0.3% • Goodreproduciblityin double readout. Inconsistency ~0.3% related to coherent SEU

  9. Normal SEU chip 27, run 53, Vdda=1.4V-0.1V, 5Mhz SRreadout SEU increase to compare to Vdda=1.5 V

  10. Normal SEU chip 28, run 53, Vdda=1.4V-0.1V, 5Mhz SRreadout SEU increase to compare to Vdda=1.5 V

  11. Normal SEU chip 27, run 54, Vdda=1.4V-0.1V, 1Mhz SRreadout SEU very close to 5 MhZ

  12. Normal SEU chip 28, run 54, Vdda=1.4V, 1Mhz SRreadout SEU slightly decrease to compare to 5 MhZ due to couple of events at 30-40 seus

  13. Radiation monitoring and GR • Malte pointed out that Power OFF/ON cycle after chip configuration, but before start primitives helps to get out GR errors. Explanations ??? This feature did not changed after reducing Idda • After reducing Idda much less errors in Service Record • No GR errors observed in normal runs with configuration every spill • No GR errors observed in runs without configurations every spill • Typical rate of PRD in normal position (13.5 mm from beam axis 0-5 counts/spill) • We will take more GR data with beam pointed to GR this week where PRD counts 90-200 counts/spill , zero without beam

  14. Conclusions • Reducing Idda and voltage drop in the cables solve the problemcoherent seu’s • New pixel latches (type B) looks very good • Low Vdda increase normal SEU and creates coherent SEUs with discrepancies in double readout • 1 MhZ SR readout slightly reduce coherent errors to compare to 5 Mhz • Vdda dependence of PR and GR SEU errors under studies with higher statistics • More runs at PRD position needed this week

  15. Spare

  16. Measurements • Two FE-I4 chips installed in the PS beam Irrad3 • Chip ID28 (PC marslhc) • Chip ID27 (PC marnach) • Also chip SEU3D installed • Order in the beam ID27,ID28,SEU3D • Al foils on ID27 and SEU3 • Orientation: EOC on the top, beam traverse first PCB, second the chips • Horizontal beam position in the center (columns 39/40) • Vertical beam position 5mm down from the center (far from EOC) • Beam size 12x12 mm • Start beam Thursday 12 may 2011

  17. Beam properties • Supercycle with 36x1.2=43.2 sec period • But sometimes is changing • Typical 2 bunches of 40 x 10 10 protons • But sometimes 3-4 bunches • Typical bunch positions: 4, 6,14,26 • Bunch length 400 msec • One iteration 2 (or 3) supercycles, 2-4 bunches per supercycle

  18. Timing Problems • Syncronize with Spill signal instead of CPS cycle • Delete time stamps, DCS voltages and currents • Reduce readout to one DC per Spill • Result: able to readout without super-positions with the beam (except sporadic spills)

  19. Timing Problems • Joern propose to write one RootDB file per spill, gain factor two in time • Since this weekend we switched to this mode • In this mode we have the time to double the readout and write the time stamp, so we can in principle correlate with beam information files • Software not yet ready for large volume analysis in this mode (handle of hunreds of files per run)

  20. Measurement of beam profile by diode (Maurice Glaser)

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