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Receiver Systems Status

Receiver Systems Status. 20 January 2009 Canberra Mark Waterson, ANU. Subsystems:. Digital Receiver (RRI) ADFB - Analog to Digital & Filter Bank (2) AGFO – Aggregation & Fiber Optic (1) Node M&C Arcom Single Board Computer (SBC) Diamond Systems GPIO card

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Receiver Systems Status

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  1. Receiver Systems Status 20 January 2009 Canberra Mark Waterson, ANU

  2. Subsystems: • Digital Receiver (RRI) • ADFB - Analog to Digital & Filter Bank (2) • AGFO – Aggregation & Fiber Optic (1) • Node M&C • Arcom Single Board Computer (SBC) • Diamond Systems GPIO card • ATIM – Antenna Tile Interface Module • ATIF – Antenna Tile Interface Filter (8) • ASC – Analog Signal Conditioning (2) • Chassis, Fans, & Power Supplies • Thermal sensor interface cards (2)

  3. Current Hardware Status* • N1 - operational at MRO • N4 – operational at MRO • N2 – repaired, enroute to Haystack • N3 – operational at RRI • * issues with BF coms affect all • * ATIF Walsh channels not fully tested

  4. Packaging & cooling Clock system Control Software (or lack thereof) Beamformer interface Rev2 pcb modifications Digital Receiver development Current Issues:

  5. Packaging & Cooling – PSI (Perth) • Preliminary design in progress • Clock system design/prototype • (CfA, ??) Preparing quotes for design/construct • Rev2 boards • ASC gain/filter, connector (mfw) • ATIM reconfigure (PSI/mfw/?) • Backplane? (PSI/RRI)

  6. Software • “Core” control software • Basic “bit-flipping” routines exist • “Robust” framework defined but needs work • Some DigiRec status features still need work • Interface between Central M&C and node • ICD defined, but not implemented completely • Ed Morgan presently working (on Node2 )

  7. Beamformer Control Interface • Requirements: • Communications • Power control & distribution • (Lightning protection) • “ATIF/BTIF” boards – existing, need fixes • “Data-over-Coax” – proto being built

  8. ATIF/BTIF Interface • Artwork faults appear to be solved in current-generation boards – OK • Filter components were incorrect on some boards, we think all fixed • 48v DC current draw • issue with ATIM component identified, will need mod to board • Fix/mod for Beamformers designed

  9. BF Long-cable communication • History: • Haystack never able to reliably drive long cables, even at 100Hz • ANU never able to reliably read back temperature or checksum • ANU has checked signal fidelity, appears clean (with correct parts) at 100KHz & 200m • Work at site this week: • MIT-Haystack tester blew up • Some BFs tested with internal read-back board • Short & long-cable waveforms recorded • Readback data saved from SBC coms • >> no consistent, proper operation observed! • Repeatedly observed BF not resetting on message start, conflicts with ICD • Errors with both long and short cables • Some ATIF dependency • DID read back correct temperature & saw internal “ok” with SBC software – ONCE…

  10. Data and clock waveforms Long cables, measured at BF end (geraldton)

  11. ANU Bench tests:

  12. Clock & data waveforms

  13. checksum & temperature

  14. Lab testing (ANU) • => BF cpld seems to be missing data bits (or clocks) • Causes checksum & temperature errors seen • Will cause tile mis-pointing • Haystack to confirm, look at BF cpld • Walsh transition drive • Waveforms confirm expectation • Impact of driver faults

  15. Walsh-sw transitions

  16. Walsh switching

  17. ATIF common-mode offsets • MAX232 IC failures, usually seems to be drive side, (but hard to be sure) • Mostly Receiver end, again not enough data • …why??? • Common-mode voltage difference between BF and Receiver exceeds chip supply, turns on/burns out protection diodes • Added ground conductors + internal tie reduced problem (2nd Nov trip), may be solution

  18. ATIF re-design? • Real problem – drive & receive circuits do not share same “ground” reference, so not possible to define/clamp voltages • Solution: isolation – optical or transformer • Opto-isolated 232 drivers • more-or-less same footprint as existing driver • Well-understood drop-in circuit fix • ATIF/BTIF board revision required • Transformer – • already available in “manchester” version of existing design • Requires mods to add encode/decode to data path (design done) • Capacitive – e.g. Eric/Roger’s serial data system?

  19. BF Interface – now what? • Soon (32T): • Complete & test “D-O-C” interface • Revision of protocol to echo back BF data suggested: • Allows SBC to confirm pointing data bits • Simple changes to both cpld code • Not compatible with D-O-C interface… • Settle ATIF (common-mode) and ATIM revisions • Build & verify interface testers using field hardware (SBC, ATIM, ATIF) so everybody uses same platform to test • Haystack visit to resolve? • Decision dates?

  20. ASC High-pass filter • Existing commercial highpass filter causes aliasing • Custom design needed to optimize MWA performance • ~ not trivial – • Fc = 300MHz, <<3dB desired • Fstop = 330MHz, >30dB++ attenuation req’d • -> Lark, Minicircuits, …? Possible vendors • footprint change impacts board layout

  21. LFCN-225 filter plot

  22. LFCN-225 filter data

  23. Receiver Development – Now What? • Complete software – science can’t be done now • Revise hardware – • BFcoms DNW • Production revisions – • ASC, ATIM, BF interface changes • Field package design • fiber data/clocks, thermal system, etc needed to get to CDR

  24. Decisions, decisions… • Cooling system capacity • trade cheaper cooling solution (=>loss of high-temperature ops time) for more tiles? • Assembly & test effort • Trade servicability (design effort/$) for test ease/ modularity • Reliability • Interfaces, operating temperature, etc vs cost & complexity

  25. Existing ATIF problems vs. lightning… • Return path to case (faraday cage) for transient protection should have been through standoffs at ATIF board corners - BUT – boards mounted on connector only! • Cable shield not connected to connector body -> no faraday shielding…

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