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IC-EMC a Demonstration Freeware for Predicting Electromagnetic Compatibility of Integrated Circuits

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IC-EMC a Demonstration Freeware for Predicting Electromagnetic Compatibility of Integrated Circuits

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    1. IC-EMC a Demonstration Freeware for Predicting Electromagnetic Compatibility of Integrated Circuits Alexandre BOYER, Etienne SICARD alexandre.boyer@insa-toulouse.fr http://www.ic-emc.org

    3. Summary

    4. 4 1. EMC of IC Issues Simulation approaches for Electromagnetic Compatibility (EMC) evaluation have become critical to shorten design cycles of modern integrated circuits (IC). Including reduction techniques in the early design phases and simulating the parasitic emission or susceptibility to EMI before fabrication requires efficient IC models, adequate tools and EMC aware engineers. Models related to EMC start appearing, as well as specific tools to handle the EMC behaviour of the IC.However, the knowledge on EMC at component level is still a matter of a few experts. Real-case measurements and models are mostly confidential, which jeopardize the share of general knowledge on this topic. Moreover, EMC education in university or industry requires not only formal courses based on specific books, but also trainings based on real cases. In order to provide a unique tool only dedicated to the simulation of emission and susceptibility prediction at integrated circuit level and a training tool, we have developed IC-EMC The aim of this presentation is to detail philosophy of this tool and the main simulation features of IC-EMC. Simulation approaches for Electromagnetic Compatibility (EMC) evaluation have become critical to shorten design cycles of modern integrated circuits (IC). Including reduction techniques in the early design phases and simulating the parasitic emission or susceptibility to EMI before fabrication requires efficient IC models, adequate tools and EMC aware engineers. Models related to EMC start appearing, as well as specific tools to handle the EMC behaviour of the IC.However, the knowledge on EMC at component level is still a matter of a few experts. Real-case measurements and models are mostly confidential, which jeopardize the share of general knowledge on this topic. Moreover, EMC education in university or industry requires not only formal courses based on specific books, but also trainings based on real cases. In order to provide a unique tool only dedicated to the simulation of emission and susceptibility prediction at integrated circuit level and a training tool, we have developed IC-EMC The aim of this presentation is to detail philosophy of this tool and the main simulation features of IC-EMC.

    5. 2. What is IC-EMC The philosophy of IC-EMC is to provide a free demonstrator for EMC of ICs simulation, which uses non-confidential information and standard models (ICEM, IBIS, ICIM) to enhance exchange of information.The philosophy of IC-EMC is to provide a free demonstrator for EMC of ICs simulation, which uses non-confidential information and standard models (ICEM, IBIS, ICIM) to enhance exchange of information.

    6. 2. What is IC-EMC IC-EMC is a demonstrating software aiming at predicting EMC at IC level. It is composed of an electric circuit schematic editor, an interface to the analog simulator WinSPICE, derived from SPICE Berkeley, and a set of post-processing tools. Moreover it provides a library of elements to build IC and EMC models, various examples of real case EMC measurement and simulation of ICs, and a set of small EMC applications. Initially, IC-EMC was dedicated to simulate parasitic emissions of ICs, but innovative parts have been proposed. Let’s see the different EMC post-processing tools provided by IC-EMC.IC-EMC is a demonstrating software aiming at predicting EMC at IC level. It is composed of an electric circuit schematic editor, an interface to the analog simulator WinSPICE, derived from SPICE Berkeley, and a set of post-processing tools. Moreover it provides a library of elements to build IC and EMC models, various examples of real case EMC measurement and simulation of ICs, and a set of small EMC applications. Initially, IC-EMC was dedicated to simulate parasitic emissions of ICs, but innovative parts have been proposed. Let’s see the different EMC post-processing tools provided by IC-EMC.

    7. This picture shows the main screen of the software, which is a schematic editor. A task bar proposes the main postprocessing tools like : emission prediction, near field simulation, immunity simulation, Z simulation, IBIS interface.This picture shows the main screen of the software, which is a schematic editor. A task bar proposes the main postprocessing tools like : emission prediction, near field simulation, immunity simulation, Z simulation, IBIS interface.

    8. Fisrt, IC-EMC proposes an editor of IBIS file. IBIS is a key file for EMC of ICs since it is a common and standard format used to exchange information about I/Os and package electrical parasitics. Information provided by IBIS are essential for I/O emission and susceptibility prediction. From IBIS file, IC-EMC proposes different screens to display I(V) characteristics of I/Os, rising/falling waveform of I/Os. These data allows the creation of equivalent buffer model. Moreover, by adding some keywords in IBIS, a 3D viewer displays simplified geometrical models of package. This tool is useful because it allows a view of pin placement, like supply pins, and a first order approximation of package electrical parasitics.Fisrt, IC-EMC proposes an editor of IBIS file. IBIS is a key file for EMC of ICs since it is a common and standard format used to exchange information about I/Os and package electrical parasitics. Information provided by IBIS are essential for I/O emission and susceptibility prediction. From IBIS file, IC-EMC proposes different screens to display I(V) characteristics of I/Os, rising/falling waveform of I/Os. These data allows the creation of equivalent buffer model. Moreover, by adding some keywords in IBIS, a 3D viewer displays simplified geometrical models of package. This tool is useful because it allows a view of pin placement, like supply pins, and a first order approximation of package electrical parasitics.

    9. An other tool is proposed to obtain more accurate package electrical model. This tool, which is still under development, contains a package layout editor to detail complex package routings and a partial element extractor based on quasi-static approximation. An other tool is proposed to obtain more accurate package electrical model. This tool, which is still under development, contains a package layout editor to detail complex package routings and a partial element extractor based on quasi-static approximation.

    10. 4. Emission Prediction The heart of IC-EMC is the simulation of parasitic emission of an IC and the comparison the results with conducted and radiated mode measurements, according to international standard methods described in IEC 61967, more specifically 1/150 O, TEM/GTEM methods and near field scan. Simulation of near field emission requires specific flow and tool. The heart of IC-EMC is the simulation of parasitic emission of an IC and the comparison the results with conducted and radiated mode measurements, according to international standard methods described in IEC 61967, more specifically 1/150 O, TEM/GTEM methods and near field scan. Simulation of near field emission requires specific flow and tool.

    11. 4. Emission Prediction The global flow for emission prediction using IC-EMC and WinSpice is outlined in this figure. Models are composed of the core model (detailed by ICEM), I/O and package model (detailed by IBIS) and measurement environment model (PCB, measurement set-up). Using WinSpice, the circuit is simulated in time-domain to get the on-chip and off-chip current/voltage variations. Then a Fast Fourier Transform (FFT) algorithm to obtain emission spectrum, which can be finally compared with measurement information to confirm the validity of the model and tune the elements of the model if necessary.The global flow for emission prediction using IC-EMC and WinSpice is outlined in this figure. Models are composed of the core model (detailed by ICEM), I/O and package model (detailed by IBIS) and measurement environment model (PCB, measurement set-up). Using WinSpice, the circuit is simulated in time-domain to get the on-chip and off-chip current/voltage variations. Then a Fast Fourier Transform (FFT) algorithm to obtain emission spectrum, which can be finally compared with measurement information to confirm the validity of the model and tune the elements of the model if necessary.

    12. 4. Emission Prediction On this slide, an example of an ICEM model of a microcontroller is proposed to predict radiated emission in GTEM cell. It is composed of the core model, the ground network model and a switching buffer. A SPICE netlist is built under IC-EMC and a SPICE transient simulation is done. At the end, a FFT is applied on time wave form and the simulated spectrum is compared with the measurement. On this slide, an example of an ICEM model of a microcontroller is proposed to predict radiated emission in GTEM cell. It is composed of the core model, the ground network model and a switching buffer. A SPICE netlist is built under IC-EMC and a SPICE transient simulation is done. At the end, a FFT is applied on time wave form and the simulated spectrum is compared with the measurement.

    13. The near-field scan method has been developed to perform near-field electromagnetic emission map. It allows identifying and localizing radiating sources at the surface of a PCB or an IC. Compared to the previous emission simulation, it requires a specific simulation flow, because geometrical information about radiating elements are necessary. The key assumption made for the near-field prediction is that leads and bonding of package are considered as the main radiated elements at IC level. Therefore a model of IC package is required to predict IC near-field radiated emission. Geometrical elementary information added in IBIS file enable package model construction. The near-field scan method has been developed to perform near-field electromagnetic emission map. It allows identifying and localizing radiating sources at the surface of a PCB or an IC. Compared to the previous emission simulation, it requires a specific simulation flow, because geometrical information about radiating elements are necessary. The key assumption made for the near-field prediction is that leads and bonding of package are considered as the main radiated elements at IC level. Therefore a model of IC package is required to predict IC near-field radiated emission. Geometrical elementary information added in IBIS file enable package model construction.

    14. On this slide, an example of an ICEM model of a microcontroller is proposed to predict the magnetic near field. It is composed of the core model, the ground network model and a switching buffer. First, pins responsible of the near field radiation are identified and placed from IBIS file data. A SPICE netlist is built under IC-EMC and a SPICE transient simulation is done. Then, a FFT is applied on time wave form and H field radiated by the radiated leads is computed. Finally, the simulated near field map is compared with the measured one.On this slide, an example of an ICEM model of a microcontroller is proposed to predict the magnetic near field. It is composed of the core model, the ground network model and a switching buffer. First, pins responsible of the near field radiation are identified and placed from IBIS file data. A SPICE netlist is built under IC-EMC and a SPICE transient simulation is done. Then, a FFT is applied on time wave form and H field radiated by the radiated leads is computed. Finally, the simulated near field map is compared with the measured one.

    15. 6. Susceptibility Prediction IC-EMC also performs susceptibility simulations of an IC to external radiofrequency interference (RFI) and compares the results with conducted and radiated mode measurements according to international standard methods IEC 62132, more specifically DPI, BCI and TEM/GTEM methods.IC-EMC also performs susceptibility simulations of an IC to external radiofrequency interference (RFI) and compares the results with conducted and radiated mode measurements according to international standard methods IEC 62132, more specifically DPI, BCI and TEM/GTEM methods.

    16. To build the model of the DUT aggression, we rely on package information given by IBIS, core model given by ICEM, and the injection path model including the RFI generator, the cable, the coupler the coupling capacitance and all the tracks on the PCB on which the tested component is mounted. The disturbance level is increased linearly for a given frequency during all the simulation duration thanks to a sinusoidal programmable source. At the end of the simulation, values of forward and reflected powers are extracted when the defined susceptibility criterion is reached. The predicted susceptibility threshold is then built by iterating this process for several frequencies. To build the model of the DUT aggression, we rely on package information given by IBIS, core model given by ICEM, and the injection path model including the RFI generator, the cable, the coupler the coupling capacitance and all the tracks on the PCB on which the tested component is mounted. The disturbance level is increased linearly for a given frequency during all the simulation duration thanks to a sinusoidal programmable source. At the end of the simulation, values of forward and reflected powers are extracted when the defined susceptibility criterion is reached. The predicted susceptibility threshold is then built by iterating this process for several frequencies.

    17. 6. Susceptibility Prediction This slide presents an example of model of susceptibility prediction for an I/O port of a 16-bit microcontroller to a conducted disturbance. Several parts are essential for the accurate modeling of the IO susceptibility. The RF disturbance flows from the RF source to the amplifier, through the coupler, the DPI capacitor, the printed-circuit-board tracks, the package lead, bonding and eventually to the buffer. Results are presented in terms of forward power versus frequency. The maximum injected power is around 25 dBm. The simulation exhibits very similar values to the measurements. The on-chip buffer is connected to its own supply network which propagates the injected noise within all the circuit. This slide presents an example of model of susceptibility prediction for an I/O port of a 16-bit microcontroller to a conducted disturbance. Several parts are essential for the accurate modeling of the IO susceptibility. The RF disturbance flows from the RF source to the amplifier, through the coupler, the DPI capacitor, the printed-circuit-board tracks, the package lead, bonding and eventually to the buffer. Results are presented in terms of forward power versus frequency. The maximum injected power is around 25 dBm. The simulation exhibits very similar values to the measurements. The on-chip buffer is connected to its own supply network which propagates the injected noise within all the circuit.

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