ELEN 468 Advanced Logic Design

1. ELEN 468Advanced Logic Design Lecture 27 Gate and Interconnect Optimization ELEN 468 Lecture 27

2. MOS Transistor Technology gate gate drain source source n n p p n well p substrate s d g g s d ELEN 468 Lecture 27

3. I-V Characteristics • Cutoff region • Vgs < Vt • Ids = 0 • Linear region • Vgs > Vt, 0 < Vds < Vgs-Vt • Ids = B[(Vgs-Vt)Vds – V2ds/2] • Saturation region • Vgs > Vt, 0 < Vgs-Vt < Vds • Ids = B(Vgs-Vt)2/2 • B = a W/L d g s Ids Vds ELEN 468 Lecture 27

4. Switching Characteristics Vin Vdd in out d t Vout Ids t Vds tfall tdelay ELEN 468 Lecture 27

5. Falling and Rising Procedure Input rising Input falling Vdd Vdd Vdd Vdd out out out out Saturation Linear Linear Saturation ELEN 468 Lecture 27

6. Falling Time • Falling time = t1 + t2 • t1 = Vout drops from 0.9Vdd to Vdd-Vt • t2 = Vout drops from Vdd-Vt to 0.1Vdd • Falling time = rising time ≈ k C / (B Vdd) • Delay ≈ Falling time / 2 ELEN 468 Lecture 27

7. Cascaded Inverters k 1 2 3 • p: stage ratio • sizei+1 = p ● sizei • Ri+1 = Ri / p • Ci+1 = p ● Ci CL ELEN 468 Lecture 27

8. Delay of Cascaded Drivers • Delay between stage i and i+1 Ri ● Ci+1 = p ● Ri ● Ci • Total delay from stage 1 to stage k pR1C1 + pR2C2 + … + pRk-1Ck-1 + RkCL = pR1C1 + pR1C1 +…+ pR1C1 + R1CL / pk-1 = (k-1)pR1C1 + R1CL / pk-1 ELEN 468 Lecture 27

9. Minimum Delay Stage Ratio • A = (k-1)●R1●C1, B = R1●CL • t = A●p + B●p1-k • Let derivative t’ = 0 • A + (1-k)●B●p-k = 0 • pk = (k-1) ●B/A = CL / C1 • p = [CL / C1]1/k ELEN 468 Lecture 27

10. Optimal Number of Stages • CL = C1 pk • k = ln(CL/C1) / ln p • t = k●p●R1●C1 = (ln (CL/C1) /lnp – 1)●p●R1●C1 • Delay t reaches minimum when p ≈ 2.72 ELEN 468 Lecture 27

11. Driver Sizing ELEN 468 Lecture 27

12. Combine Buffering and Driver Sizing Directly? Min delay ELEN 468 Lecture 27

13. Impact To Previous Stage Previous stage Current stage Small load Large delay Cd Large load Small delay ELEN 468 Lecture 27

14. Input Load Penalty • Penalty = delay of min delay buffer chain driving Cd Min buffer Cd ELEN 468 Lecture 27

15. Driver Sizing Considering Impact to Previous Stage Previous stage Current stage Small load Large delay Large penalty Cd Large load Small delay ELEN 468 Lecture 27

16. Driver Sizing in Van Ginneken’s Algorithm Treat the buffer chain as a part of the net Length = 0 Run van Ginneken’s algorithm with fixed driver and min sized buffer ELEN 468 Lecture 27

17. Dependence on Steiner Tree Timing critical Timing critical ELEN 468 Lecture 27

18. Rectilinear Steiner Minimum Tree • Given a signal net, find the best tree connecting them • Minimize wire area • Wire area implies • Cost • Capacitive load  delay • Find Steiner minimum tree Spanning tree Steiner node Steiner tree ELEN 468 Lecture 27

19. Hanan Grid and Hanan Theorem • Hanan grid • Draw vertical and horizontal lines through all pins • Hanan Theorem • There is always a Steiner minimum tree on Hanan grid ELEN 468 Lecture 27

20. Iterative 1-Steiner Algorithm • In each step, add one Steiner node such that the spanning tree is minimized ELEN 468 Lecture 27

21. Area or Radius? Radius: the longest source-sink path length • Dijkstra’s shortest path tree • Short path to sinks • Large total wire length • Prim’s minimum spanning tree • Small total wire length • Long path to sinks ELEN 468 Lecture 27

22. Area Radius Trade-off • Find a solution in middle • Not too much area • Not too long radius • How to find an ideal point? ELEN 468 Lecture 27

23. d(i,j) Prim’s and Dijkstra’s Algorithms • d(i,j): length of edge (i, j) • p(i): length of path from source to i • Prim: min d(i,j) Dijkstra: min d(i,j) + p(i) p(i) i j ELEN 468 Lecture 27

24. The Prim-Dijkstra Trade-off • Prim: add edge minimizing d(i,j) • Dijkstra: add edge minimizing p(i) + d(i,j) • Trade-off: c●p(i) + d(i,j) for 0 ≤c ≤ 1 • When c=0, trade-off = Prim • When c=1, trade-off = Dijkstra ELEN 468 Lecture 27

25. Spanning Tree → Steiner Tree ELEN 468 Lecture 27

26. Rectilinear Steiner Arborescence (RSA) • Every source-sink path is the shortest • Minimum total wire length ELEN 468 Lecture 27

27. RSA Heuristic • Assume all sinks in first quadrant • Initially, each sink is a subtree • Iteratively merge or grow subtrees toward the source ELEN 468 Lecture 27

28. Merge Grow RSA Example ELEN 468 Lecture 27

29. Merging Rule In RSA Heuristic • Iteratively • Find subtrees rooted at p and q maximizing min(xp, xq) + min (yp, yq) • Merge them to a new subtree rooted at r = (min(xp, xq), min (yp, yq)) ELEN 468 Lecture 27

30. 1 2 3 4 5 6 RSA Diagonal Line Sweep ELEN 468 Lecture 27

31. Buffered A-Tree ELEN 468 Lecture 27