ELEN 468 Advanced Logic Design

1. ELEN 468Advanced Logic Design Lecture 2 Hardware Modeling ELEN 468 Lecture 2

2. Overview • Verilog modules • Verilog primitives • Structural descriptions • Behavioral descriptions • Hierarchical design • Language conventions ELEN 468 Lecture 2

3. a sum b c_out_bar c_out Verilog Module module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule • Description of internal structure/function • Implicit semantic of time associated with each data object/signal • Implementation is hidden to outside world • Communicate with outside through ports • Port list is optional • Achieve hardware encapsulation ELEN 468 Lecture 2

4. a sum Add_half b c_out Behavioral Description module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment endmodule Concatenation ELEN 468 Lecture 2

5. Module Instantiation • Accomplished by entering • Module name as a module item within a parent module • Signal identifiers at appropriate ports • Module instantiation needs a module identifier • A module is never declared within another module • The order of ports in instantiation usually matches the order in module declaration ELEN 468 Lecture 2

6. Design a Full Adder a + b = a(b+b’) + (a+a’)b = ab + ab’ + a’b sumHA = a  b c_outHA = a • b sumFA = a  b  c_in c_outFA = a • b + b • c_in + a • c_in sumFA = (a  b)  c_in c_outFA = (a  b) • c_in + a • b ab + bc + ac = ab + (a+b)c = ab + (a b+ab)c = ab + a b c+abc = ab + (a b)c ELEN 468 Lecture 2

7. Add_half Full Adder  2 Half Adders sumHA = a  b c_outHA = a • b sumFA = (a  b)  c_in c_outFA = (a  b) • c_in + a • b c_in (a  b)  c_in a ab (ab)•c_in Add_half b a•b (a  b) • c_in + a • b ELEN 468 Lecture 2

8. Add_half Module instance name Full Adder in Verilog sum c_in (a  b)  c_in module Add_full ( sum, c_out, a, b, c_in ); // parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Add_half M1 ( w1, w2, a, b ); Add_half M2 ( sum, w3, w1, c_in ); // child module or ( c_out, w2, w3 ); // primitive instantiation endmodule w1 w3 a ab (ab)•c_in Add_half c_out w2 b a•b (a  b) • c_in + a • b ELEN 468 Lecture 2

9. Verilog Primitives • Basic element to build a module, such as nand, nor, buf and not gates • Never used stand-alone in design, must be within a module • Pre-defined or user-defined • Identifier (instance name) is optional • Output is at left-most in port list • Default delay = 0 ELEN 468 Lecture 2

10. Symmetric Delay Assignment module AOI_4 ( y, x1, x2, x3, x4 ); input x1, x2, x3, x4; output y; wire y1, y2; and #1 ( y1, x1, x2 ); and #1 ( y2, x3, x4 ); nor #1 ( y, y1, y2 ); endmodule x1 y1 x2 y x3 y2 x4 ELEN 468 Lecture 2

11. Falling time Rising time Asymmetric Delay Assignment module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); endspecify endmodule Min delay Typical delay Max delay ELEN 468 Lecture 2

12. Smart Primitives module nand3 ( O, A1, A2, A3 ); input A1, A2, A3; output O; nand ( O, A1, A2, A3 ); endmodule Same primitive can be used to describe for any number of inputs This works for only pre-defined primitives, not UDP ELEN 468 Lecture 2

13. Explicit Structural Descriptions module AOI_4 ( y, x1, x2, x3, x4 ); input x1, x2, x3, x4; output y; wire y1, y2; and #1 ( y1, x1, x2 ); and #1 ( y2, x3, x4 ); nor #1 ( y, y1, y2 ); endmodule x1 y1 x2 y x3 y2 x4 ELEN 468 Lecture 2

14. module nand2_RTL ( y, x1, x2 ); input x1, x2; output y; assign y = x1 ~& x2; endmodule module nand2_RTL ( y, x1, x2 ); input x1, x2; output y; wire y = x1 ~& x2; endmodule Implicit Structural Description Explicit continuous assignment Implicit continuous assignment Continuous assignment – Static binding between LHS and RHS No mechanism to eliminate or alter the binding ELEN 468 Lecture 2

15. Multiple Instantiations module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; output y1, y2, y3; nand #1 G1(y1, a1, a2, a3), (y2, a2, a3, a4), (y3, a1, a4); endmodule The delay element #1 is effective for all instances ELEN 468 Lecture 2

16. Multiple Assignments module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; output y1, y2, y3; assign #1 y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a4; endmodule ELEN 468 Lecture 2

17. Structural Connections module child( a, b, c ); … endmodule module parent; wire u, v, w; child m1( u, v, w ); child m2( .c(w), .a(u), .b(v) ); child m3( u, , w ); endmodule • By order • By name • Empty port ELEN 468 Lecture 2

18. module and4( y, x ); input [3:0] x; output y; assign y = & x; endmodule module Flip_flop ( q, data_in, clk, rst ); input data_in, clk, rst; output q; reg q; always @ ( posedge clk ) begin if ( rst == 1) q = 0; else q = data_in; end endmodule Behavioral Descriptions: Data Flow ELEN 468 Lecture 2

19. Optional name Enable “disable” Behavioral Descriptions: Algorithm-based module and4_algo ( y, x ); input [3:0] x; output y; reg y; integer k; always @ ( x ) begin: and_loop y = 1; for ( k = 0; k <= 3; k = k+1 ) if ( x[k] == 0 ) begin y = 0; disable and_loop; end end endmodule x[0] or x[1] or x[2] or x[3] ELEN 468 Lecture 2

20. Structural Behavioral Description Styles • Explicit structural • Implicit structural • Explicit continuous assignment • Implicit continuous assignment • Data flow/RTL • Algorithm-based ELEN 468 Lecture 2

21. Add_full Add_half M1 M2 Add_half Add_half or xor xor nand nand not not Hierarchical Description M2 sum c_in M1 a Add_half c_out b Nested module instantiation to arbitrary depth ELEN 468 Lecture 2

22. Structured Design Methodology • Design: top-down • Verification: bottom-up • Example 2.18 in textbook pg 45 ELEN 468 Lecture 2

23. Arrays of Instances rst module flop_array(q, in, clk, rst); input [7:0] in; input clk, rst; output [7:0] q; Flip_flop M[7:0] (q, in, clk, rst); endmodule module pipeline(q, in, clk, rst ); input [7:0] in; input clk, rst; output [7:0] q; wire [23:0] pipe; flop_array M[3:0] ({q, pipe}, {pipe, in}, clk, rst); endmodule in[7:0] pipe[7:0] pipe[23:16] q[7:0] clk ELEN 468 Lecture 2

24. module comp(lt,gt,eq,a0,a1,b0,b1); input a0, a1, b0, b1; output lt, gt, eq; wire w1, w2, w3, w4, w5, w6, w7; or (lt, w1, w2, w3); nor (gt, lt, eq); and (w1, w6, b1); and (w2, w6, w7, b0); and (w3, w7, b0, b1); not (w6, a1); not (w7, a0); xnor (w4, a1, b1); xnor (w5, a0, b0); endmodule module comp(lt, gt, eq, a, b); input [1:0] a, b; output lt, gt, eq; assign it = ( a < b ); assign gt = ( a > b ); assign eq = ( a == b ); endmodule Verilog for Synthesis Figure 2.30 Figure 2.28 ELEN 468 Lecture 2

25. Language Conventions • Case sensitive • Instance of a module must be named • Keywords are lower-case • Comments start with “//”, or blocked by “/* */” ELEN 468 Lecture 2

26. Numbers in Verilog • Binary, decimal, octal, hex … • Table 2.2 ELEN 468 Lecture 2