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ELEN 468 Advanced Logic Design

ELEN 468 Advanced Logic Design. Lecture 14 Synthesis of Sequential Logic . Synthesis of Sequential Logic: General. Event control of a cyclic behavior must be synchronized to a single edge of a single clock always @ ( posedge clock ) Different behaviors may be synchronized to

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ELEN 468 Advanced Logic Design

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  1. ELEN 468Advanced Logic Design Lecture 14 Synthesis of Sequential Logic ELEN 468 Lecture 14

  2. Synthesis of Sequential Logic: General • Event control of a cyclic behavior must be synchronized to a single edge of a single clock always @ ( posedge clock ) • Different behaviors may be synchronized to • different clocks • or different edges of a clock • but clock periods should be same ELEN 468 Lecture 14

  3. Options for Implementing Sequential Logic • User-defined primitive • Behavior with timing controls • Instantiated library register cell • Instantiated module ELEN 468 Lecture 14

  4. Commonly Synthesized Sequential Logic • Data register • Transparent latch • Shift register • Binary counter • Finite state machine • Pulse generator • Clock generator • Parallel/serial converter … … Table 9.2, page 346 ELEN 468 Lecture 14

  5. Synthesis of Sequential UDPs • Only one synchronizing signal • Clock level – latch • Clock signal edge – flip-flop • A synthesis tool may have its own requirement • For example, may constrain the order of rows – asynchronous first ELEN 468 Lecture 14

  6. Example of Sequential UDP primitive d_flop( q, clock, d ); output q; input clock, d; reg q; table // clock d state q/next_state (01) 0 : ? : 0; // Parentheses indicate signal transition (01) 1 : ? : 1; // Rising clock edge (0?) 1 : 1 : 1; (0?) 0 : 0 : 0; (?0) ? : ? : -; // Falling clock edge ? (??) : ? : -; // Steady clock endtable endprimitive clock d q d_flop ELEN 468 Lecture 14

  7. Synthesis of Latches • Latches are incurred at • Incompletely specified input conditions for • Continuous assignment -> mux with feedback • Edge-triggered cyclic behavior -> gated datapath • Level-sensitive cyclic behavior -> latch • Feedback loop ELEN 468 Lecture 14

  8. Latch Resulted from Unspecified Input State module myMux( y, selA, selB, a, b ); input selA, selB, a, b; output y; reg y; always @ ( selA or selB or a or b ) case ( {selA, selB} ) 2’b10: y = a; 2’b01: y = b; endcase endmodule b selA’ en selB y selA latch selB’ a ELEN 468 Lecture 14

  9. Latch Resulted from Feedback Loop module latch1 ( out, in, enable ); input in, enable, output out; reg out; always @ ( enable ) begin if ( enable ) assign out = in; else assign out = out; end endmodule enable in out mux ELEN 468 Lecture 14

  10. Synthesis of Edge-triggered Flip-flops • A register variable in a behavior might be synthesized as a flip-flop if • It is referenced outside the scope of the behavior • Referenced within the behavior before it is assigned value • Assigned value in only some branches of the activity ELEN 468 Lecture 14

  11. Event Control Sensitive to Multiple Signal Edges module DReg ( out, in, clock, reset ); input in, clock, reset; output out; register out; always @ ( posedge clock or posedge reset ) begin if ( reset == 1’b1 ) out = 0; else out = in; end endmodule An if statement decode control signals at the beginning of the behavior ELEN 468 Lecture 14

  12. Registered Combinational Logic module reg_and ( y, a, b, c, clk ); input a, b, c, clk; output y; reg y; always @ ( posedge clk ) y = a & b & c; endmodule clk a y b c ELEN 468 Lecture 14

  13. Shift Register module shift4 ( out, in, clock, reset ); input in, clock, reset; output out; reg [3:0] data_reg; assign out = data_reg[0]; always @ ( negedge reset or posedge clock ) begin if ( reset == 1’b0 ) data_reg = 4’b0; else data_reg = { in, data_reg[3:1] }; end endmodule Figure 9.10, page 361 ELEN 468 Lecture 14

  14. Counter module ripple_counter ( count, clock, toggle, reset ); input clock, toggle, reset; output [3:0] count; reg [3:0] count; wire c0, c1, c2; assign c0 = count[0]; assign c1 = count[1]; assign c2 = count[2]; always @ ( posedge reset or posedge clock ) if ( reset == 1’b1 ) count[0] = 1’b0; else if ( toggle == 1’b1 ) count[0] = ~count[0]; always @ ( posedge reset or negedge c0 ) if ( reset == 1’b1 ) count[1] = 1’b0; else if ( toggle == 1’b1 ) count[1] = ~count[1]; always @ ( posedge reset or negedge c1 ) if ( reset == 1’b1 ) count[2] = 1’b0; else if ( toggle == 1’b1 ) count[2] = ~count[2]; always @ ( posedge reset or negedge c2 ) if ( reset == 1’b1 ) count[3] = 1’b0; else if ( toggle == 1’b1 ) count[3] = ~count[3]; endmodule Fig. 9.14 Page 366 ELEN 468 Lecture 14

  15. Synthesis of Explicit Finite State Machines • A behavior describing the synchronous activity may contain only one clock-synchronized event control expression • There is always one and only one explicitly declared state register • State register must be assigned value as an aggregate, bit select and part select assignments to state register is not allowed • Asynchronous control signals must be scalars in the event control expression of behavior • Value assigned to state register must be constant or a variable that evaluates to a constant ELEN 468 Lecture 14

  16. Comparison of Explicit and Implicit FSMs ELEN 468 Lecture 14

  17. State Encoding Example ELEN 468 Lecture 14

  18. State Encoding • A state machine having Nstates will require at least log2N bits register to store the encoded representation of states • Binary and Gray encoding use the minimum number of bits for state register • Gray and Johnson code: • Two adjacent codes differ by only one bit • Reduce simultaneous switching • Reduce crosstalk • Reduce glitch ELEN 468 Lecture 14

  19. Employ one bit register for each state Less combinational logic to decode Consume greater area, does not matter for certain hardware such as FPGA Easier for design, friendly to incremental change case and if statement may give different result for one-hot encoding Runs faster ‘define state_0 3’b001 ‘define state_1 3’b010 ‘define state_2 3’b100 One-hot Encoding ELEN 468 Lecture 14

  20. Rules for Implicit State Machines Synchronizing signals have to be aligned to the same clock edge in an implicit FSM, the following Verilog code will not synthesize … … always @ ( posedge clock ); begin a <= b; c <= d; @( negedge clock ) begin e <= f; g <= h; end end … … ELEN 468 Lecture 14

  21. Resets • Strongly recommended that every sequential circuit has a reset signal • Avoid uncertain initial states • Specification for output under reset should be complete, otherwise wasted logic might be generated ELEN 468 Lecture 14

  22. Gated Clock • Pro: reduce power consumption • Con: unintentional skew data Q flip-flop clock clock_enable ELEN 468 Lecture 14

  23. 1 a b 2 3 c Design Partitions Partition cells such that connections between partitions is minimum 1 a 2 b 3 c ELEN 468 Lecture 14

  24. Example: Sequence Detector • Single bit serial input • Synchronized to falling edge of clock • Single bit output • Assert if two or more successive 0 or 1 at input • Active on rising edge of clock Clock Input Output ELEN 468 Lecture 14

  25. State Transition Diagram State0 Start state 1/0 0/0 1/1 0/1 1/0 State1 Input 0 State2 Input 1 0/0 ELEN 468 Lecture 14

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