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ELEN 468 Advanced Logic Design

ELEN 468 Advanced Logic Design. Lecture 22 Timing Verification. General. Timing verifications should be performed at every design stage Timing verifications at early stages are not accurate as no detailed physical information available. Register. Register. Combinational Logic.

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ELEN 468 Advanced Logic Design

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  1. ELEN 468Advanced Logic Design Lecture 22 Timing Verification ELEN 468 Lecture 22

  2. General • Timing verifications should be performed at every design stage • Timing verifications at early stages are not accurate as no detailed physical information available ELEN 468 Lecture 22

  3. Register Register Combinational Logic Combinational Logic Combinational Logic Type of Timing Paths • Input -> register • Register -> register • Register -> output • Input -> output Clock ELEN 468 Lecture 22

  4. Register Register Combinational Logic Clock Scheduling LD: logic delay i j ti tj Clock ELEN 468 Lecture 22

  5. Timing Constraints CP • skewij = ti – tj <= CP – LDmax – setupmax (long path) • skewij = ti – tj >= holdmax – LDmin (short path) hold setup tj LDmin ti LDmax ELEN 468 Lecture 22

  6. Static Timing Analysis 2 7/4/-3 9/6/-3 • Arrival time: input -> output, take max • Required arrival time: output -> input, take min • Slack = required arrival time – arrival time 5/3/-2 3 11 20/17/-3 3 23/20/-3 7 2 4 4/7/3 18/18/0 8/8/0 3 11/11/0 ELEN 468 Lecture 22

  7. False Paths Max path delay = 15? [3:5, 2:3] [3:5, 2:3] [3:5, 2:3] Min, max rising Min, max falling ELEN 468 Lecture 22

  8. Dynamically Sensitized Paths c d b a ‘0’ a b c d ELEN 468 Lecture 22

  9. Gate and Wire Model C R r: resistance per unit length c: capacitance per unit length L rL cL/2 cL/2 ELEN 468 Lecture 22

  10. 2 L2 L1 1 0 C2 L3 2 rL2 3 R rL1 cL2/2+C2 0 1 C3 cL1/2 3 rL3 cL3/2+C3 (L1+L2+L3)c/2 Example of Model ELEN 468 Lecture 22

  11. Delay Estimation 2 R2 • D0 = R ( C0 + C1 + C2 + C3 ) • D1 = D0 + R1 ( C1 + C2 + C3 ) • D2 = D1 + R2 C2 • D3 = D1 + R3 C3 R R1 C2 0 1 C0 C1 R3 3 C3 ELEN 468 Lecture 22

  12. Interconnect Size Scaling • Wire width scales faster than wire height  wires are thinner and taller • Wires are placed closer • Coupling capacitance start to dominate substrate capacitance ELEN 468 Lecture 22

  13. Crosstalk Noise • Crosstalk noise may cause • Glitch and logical error • Extra propagation delay aggressor victim ELEN 468 Lecture 22

  14. Elimination of Timing Violation ELEN 468 Lecture 22

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