ITRS Public Conference Emerging Research Devices

ITRS Public ConferenceEmerging Research Devices 2011 ERD Chapter Jim Hutchby – SRC July 13, 2011

Emerging Research Devices Working Group • Hiroyugi Akinaga AIST • Tetsuya Asai Hokkaido U. • Yuji Awano Keio U. • George Bourianoff Intel • Michel Brillouet CEA/LETI • Joe Brewer U. Florida • John Carruthers PSU • Ralph Cavin SRC • An Chen GLFOUNDRIES • U-In Chung Samsung • Byung Jin Cho KAIST • Sung Woong Chung Hynix • Luigi Colombo TI • Shamik Das Mitre • Erik DeBenedictis SNL • Simon Deleonibus LETI • Bob Fontana IBM • Paul Franzon NCSU • Akira Fujiwara NTT • Christian Gamrat CEA • Mike Garner Intel • Dan Hammerstrom PSU • Wilfried Haensch IBM • Tsuyoshi Hasegawa NIMS • Shigenori Hayashi Matsushita • Dan Herr SRC • Toshiro Hiramoto U. Tokyo • Matsuo Hidaka ISTEK • Jim Hutchby SRC • Adrian Ionescu EPFL • Kiyoshi Kawabata Renesas Tech • Seiichiro Kawamura Selete • Suhwan Kim Seoul Nation U • Hyoungjoon Kim Samsung • Atsuhiro Kinoshita Toshiba • Dae-Hong Ko Yonsei U. • Hiroshi Kotaki Sharp • Mark Kryder INSIC • Zoran Krivokapic GLOBALFOUNDRIES • Kee-Won Kwon Seong Kyun Kwan U. • Jong-Ho Lee Hanyang U. • Lou Lome IDA • Hiroshi Mizuta U. Southampton • Matt Marinella SNL • Kwok Ng SRC • Fumiyuki Nihei NEC • Ferdinand Peper NICT • Yaw Obeng NIST • Dave Roberts Nantero • Barry Schechtman INSIC • Sadas Shankar Intel • Atsushi Shiota JSR Micro • Satoshi Sugahara Tokyo Tech • Shin-ichi Takagi U. Tokyo • Ken Uchida Tokyo Inst. Tech. • Thomas Vogelsang Rambus • Yasuo Wada Toyo U. • Rainer Waser RWTH A • Franz Widdershoven NXP • Jeff Welser NRI/IBM • Philip Wong Stanford U. • Dirk Wouters IMEC • Kojiro Yagami Sony • David Yeh SRC/TI • Hiroaki Yoda Toshiba • In-K Yoo SAIT • Victor Zhirnov SRC

Evolution of Extended CMOS Elements Existing technologies More Than Moore ERD-WG in Japan New technologies Beyond CMOS year

Changed Scope of Emerging Research Devices Chapter • New More-than-Moore Section added – Focused on RF • Emerging Research Memory Devices section broadened in 2011 to include: • New “Storage Class Memory” Subsection • New Memory “Select Device” Subsection • Emerging Research Logic section changed • Transitioned n-InGaAs & p-Ge alternate channel MOSFETs to PIDS & FEP. • Synchronized more closely with the Nanoelectronics Research Initiative (NRI) • Expanded technology Benchmarking section • Expanded Architecture Section

2011 ERD Chapter • Emerging Memory Devices • Emerging Logic Devices • More-than-Moore Devices • Benchmarking and Assessing Emerging Devices • Emerging Architectures

2009 Memory Technology Entries Resistive Memories • Redox Memory • Electrochemical memory • Valence change memory • Fuse/Antifuse (Thermochemical memory} • Molecular Memory • Spin Transfer Torque MRAM • Nanoelectromechanical • Nanowire PCM • Macromolecular (Polymer) Capacitive Memory • Electronic Effects Memory • Charge trapping • Metal-Insulator Transition • FE barrier effects • FeFET Memory

2011 Memory Technology Entries Resistive Memories • Redox Memory • Electrochemical memory • Valence change memory • Fuse/Antifuse (Thermochemical memory} • Molecular Memory • Spin Transfer Torque MRAM • Nanoelectromechanical • Nanowire PCM • Macromolecular (Polymer) Capacitive Memory • Electronic Effects Memory • Charge trapping • Metal-Insulator Transition • FE barrier effects • FeFET Memory

ERD/ERM Memory Technology Assessment Workshop ITRS ERD/ERM identified two emerging memory technologies for accelerated research & development: 1)STT-MRAM and 2) Redox Resistive RAM Redox Memory Cell STT-Memory Cell

Memory Hierarchy – Future Memory Challenge NVM cost/gigabyte ~ $1 Al Fazio - Intel

One Diode – One Resistor (1D1R) Memory Cell Select Device = Diode H-S. P. Wong – Stanford U.

2009 Logic Technology Tables Table 3 - Non-FET, Non Charge-based ‘Beyond CMOS’ devices _______________ Collective Magnetic Devices Moving domain wall devices Atomic Switch Molecular Switch Pseudo-spintronic Devices Nanomagnetic (M:QCA) Table 1 – Extending MOSFETs to the End of the Roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non-conventional Geometry Devices Table 2- Unconventional FETS, Charge-based Extended CMOS _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET

2011 Logic Technology Tables Table 1 – Extending MOSFETs to the End of the Roadmap ___________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Tunnel FET Non-conventional Geometry Devices Table 3 - Non-FET, Non Charge-based ‘Beyond CMOS’ Devices _______________ Spin Transfer Torque Logic Moving domain wall devices Pseudo-spintronic Devices Nanomagnetic (M:QCA) Negative Cg MOSFET All Spin Logic Molecular Switch Atomic Switch BiSFET Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Spin FET& Spin MOSFET Negative Cg MOSFET NEMS switch Excitonic FET Mott FET Tunnel FET I-MOS SET

ERD/ERM Logic Technology Recommended Focus: Carbon-based Nanoelectronics – Carbon Nanotubes and Graphene Graphene quantum dot Band gap engineered Graphene nanoribbons FET (Manchester group) Nonconventional Devices Graphene Veselago lense Graphene pseudospintronics Graphene Spintronics Son et al.Nature (07) Cheianov et al.Science (07) Trauzettel et al.Nature Phys. (07) Conventional Devices P. Kim – Columbia U.

rf wave LNA ADC 011001010… LO control PA DAC Wireless underlying architecture / functions Higher level function Intermediate levelfunction nanoradio filter oscillator mixer LO Lower level functions • spin-torque oscillator • graphene NEMS nanoresonator

PreferredCorner PreferredCorner PreferredCorner Benchmarking NRI Median Switch Characteristics ENERGY DELAY AREA All 3 metrics responding consistently – energy and area superiority. Little change in the energy delay product.

Four Architectural Projections • Hardware Accelerators execute selected functions faster than software performing it on the CPU. • Alternative switches often exhibit emergent, idiosyncratic behavior. They also maybe non-volatile. We should exploit them. • CMOS is not going away anytime soon. • New switches may improve high utilization accelerators

Matching Logic Functions & New Switch Behaviors New Switch Ideas Popular Accelerators Single Spin Spin Domain Tunnel-FETs NEMS MQCA Molecular Bio-inspired CMOL Excitonics Encrypt / Decrypt Compr / Decompr Reg. Expression Scan Discrete COS Trnsfrm Bit Serial Operations H.264 Std Filtering DSP, A/D, D/A Viterbi Algorithms Image, Graphics ? Example: Cryptography Hardware Acceleration Operations required: Rotate, Byte Alignment, EXORs, Multiply, Table Lookup Circuits used in Accel: Transmission Gates (“T-Gates”) New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay. Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.

ERD – Key Messages • New More-than-Moore Section added – Focused on RF devices • Emerging Research Memory Devices section broadened in 2011 to include: • New “Storage Class Memory” Subsection • New Memory “Select Device” Subsection • Transitioned STT-MRAM to PIDS & FEP • Introduced new memory device category – Redox RAM • Emerging Research Logic changes: • Transitioned n-InGaAs & p-Ge alternate channel MOSFETs to PIDS & FEP. • Synchronized more closely with the Nanoelectronics Research Initiative (NRI) • Expanded technology benchmarking section • Expanded Architecture Section

ITRS Public Conference Emerging Research Devices