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Multichannel integrated circuits for digital X-ray imaging with energy windowing

Multichannel integrated circuits for digital X-ray imaging with energy windowing K rzysztof Świentek Department of Nuclear Electronics FPNT, AGH Kraków K.Swientek @ftj.agh.edu.pl. Content. Introduction – multichannel ASICs Noise in MOS transistors

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Multichannel integrated circuits for digital X-ray imaging with energy windowing

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  1. Multichannel integrated circuits • for digital X-ray imaging • with energy windowing • Krzysztof Świentek • Department of Nuclear Electronics • FPNT, AGH Kraków • K.Swientek@ftj.agh.edu.pl

  2. Content • Introduction – multichannel ASICs • Noise in MOS transistors • Crosstalk in mixed–mode integrated circuits • Random matching • RX64DTH– digital imaging using silicon detectors • Measurements results – chip tutorial • Summary

  3. Introduction  multichannel ASIC SET OF SENSORS ( silicon strip detector) Input signals - small amplitude (Qin = 1400 el) - stochastic character (amplitude, time) MULTICHANNEL INTEGRATED CIRCUITS (analogue & digital blocks) LIMITS: power & area LOW LEVEL OF NOISE 6.5 mm RX64DTH UNIFORMITY OF PARAMETERS CROSSTALK digital  analogue

  4. Noise in MOS transistors 1.Thermal noise of channel saturation linear 2. Flicker noise Simulations (HSPICE) Simulations (HSPICE) NLEV=3 NLEV=2, 3 BSIM3v3 (NIMOD=2) BSIM3v3 (NIMOD=2) Measurments – short channel effects (2-10x): ( velocity saturation, hot electrons) Measurments – short channel effects ( hot electrons, RST noise)

  5. ANALOG BLOCKS DIGITAL BLOCKS GENERATION TRANSFER SILICON SUBSTRATE EFFECT CROSSTALK • Transfer: • common supply lines: parasitic inductance and resistance (Vind=LdI/dt) • common substrate: (substrateepi, VT=f(VSB), gmb) • Effects for analogue blocks: switching noise, oscillation etc. • Minimisation: • reducing the noise generation, • increasing the immunity of analogue part, • isolation techniques.

  6. L L W W D RANDOM MATCHING MATCHING - identically design devices have different parameters P=P1-P2 (P/P) Number of cases P/P [%] For MOS transistors: VT0 , ,  CMOS 0.7m - (VT0) NMOS PMOS W/L=2m/0.7m 9.72 mV 19.43 mV W/L=1500m/1.5m 0.31 mV 0.63 mV

  7. 1. Matching  bias condition differences:VT, , R a) b) 2. Reduce sensitivity - proper configuration(Kv Ci/Cj) 3. Monte-Carlo analysis using HSPICE (matching data for given technology) • 4. Symmetry in layout • bias, temperature, orientation, • common centroid geometry, unit cells, • surrounding, metal coverage

  8. X-rays current pulses 100 m PC computer data, control Silicon strip detector Integrated circuit X-ray imaging using silicon strip detectors • Key system issues: • fully parallel signal processing for all channels. • only binary information (yes/no) is extracted from each strip. • data from each channel must be stored in the local buffer for the whole measurement period. Signal 10x smaller Stochastic High Energy Physics

  9. RX64DTH -fully integrated 64-channel chip (CMOS 0.8 mm process) • RX64DTH consists of: • 64 front-end channels (preamplifier, shaper, two discriminators) • 128 pseudo-random counters (20-bit) • internal DACs: two 8-bit threshold setting and and three 5-bit for bias • internal calibration circuit (square wave 1mV-30 mV) • control logic • I/O circuit (interface to external bus) 37006500 m2

  10. V 0 t Tp 1 V V 0 t t VT-HIGH VT-LOW Single analogue channel C3 C2 C5 Shaper Preamplifier Discriminators  • Key design issues: • low noise (ENC200 el. rms, sensor ) • low power (3-5 mW/channel) • relatively fast shaping (Tp = 0.5 1s) • uniformity from channel to channel (gain, offset, noise) • immunity to switching noise

  11. V t Tp V t Preamplifier & shaper SENSOR: Cdet Idet Rbias LIMITATIONS Minimum of noise (transistor dimensions, bias) 1. POWER 2. PEAKING TIME 3. SENSOR 4. PSRR, stability, matching. Simulation HSPICE Hand calculation Measurements (bias, temp., Tp) • DAC currents • IFED • IFEDSH • ICAS Other transistors M1: 500/1 M5: 2/120 M4: 100/10 Id = 500 A

  12. V t Tp TP [s] ENC versus Peaking Time Noise types ENC – total noise ENCW – white voltage noise ENCf – 1/f voltage noise ENCi – white current noise Peaking time TP • Optimal  the lowest noise • Fast Front-end  increasing noise

  13. V 1 1 VT-HIGH t Tp 0 0 VT-LOW Discriminator – offsets, crosstalk • AC coupling • differential stage(CMRR) • hysteresis • power supply lines, guard rings

  14. Pseudo-random counters • 20 bit counters (large dynamic range of the image) • small layout area (only 8 transistor per bit) • 128 counters are grouped in the 8 blocks of 16 counters each (8 bit I/O bus to minimize the dead time)

  15. Functionality & testability Calibration circuits: Qinj=CtVcal (500 el - 13000 el) Internal DACs: threshold setting, gain, peaking time 2 x threshold 8-bit 3 x bias 5-bit 1 x calibration 4-bit • I/O circuits: • LVDS standard (command, clock) • 8-bit data bus (tristate), • 3-bit address (up to 8 chips) 6 dacs

  16. 7 2 3 4 5 6 13 10 14 11 12 Digital guard ring Analog guard ring 8 9 Digital ground Analog ground Middle ring LAYOUT - floor plan, bias lines, pads • Isolation techniques • reduce inductance (separatebias line,pads), • floor plan, bias lines • keep “clean” substrate– LVDS • RC filters • guard rings, shielding • Floor plan • preamplifier & shaper • discriminators • counters & IOs • digital outputs • control logic • calibration • bias DACs

  17. Window – threshold DAC’s • two independent DACs • common centroid matrix • mixed matrices • matching problem • need software correction Dac value [LSB] Difference between DAC HIGH and LOW Difference [mV] Difference [LSB] 7 LSB Dac value [LSB] Silicon: 3,67eV/el

  18. Noise versus ICAS & Temp VTH = 255 VTL = scan VTH = scan VTL = 255 Source Pu238 + Cu Vdet = 130 V Vdd = 4.0 V Vddd = 4.0 V Peltier element for temp. Controled Temp.

  19. Noise versus IFED • gain & offset const • window is 5 LSB • Peltier element } fast noise increasing pin-holes in detector  leakeage current dead channels because out of operating point rescue increase IFED but ...

  20. Simulation: TP & Gain as a function of IFEDSH shaper output  Impulse height • TP = 0.7 – 1 s • Impulse fall ends  4 s  200 kHz TP

  21. Gain, Offset & Noise versus IFEDSH • window is 5 LSB • Peltier element max (slow) peaking time TP min (fast)

  22. Summary • Multichannel mix-mode ASIC : • —critical parameters connected together • — looking for a golden solution • Software corrections : • —DACs problem • — differences between the chips • Noise controling : • IFED – better detector  lower noise • ICAS – the highier the beter (cooling ?) • IFEDSH – high gain gives low noise and speed • To do – measurements • — speed • — uniformity in 6-chip module

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