Digital Integrated Circuits for Communication

1. Digital Integrated Circuits for Communication Class 04

2. Sequential CMOS and NMOS Logic Circuits • Sequential logic circuits contain one or more combinational logic blocks along with memory in a feedback loop with the logic • The next state of the machine depends on the present state and the inputs • The output depends on the present state of the machine and perhaps also on the inputs • Mealy machine: output depends only on the state of the machine • Moore machine: the output depends on both the present state and the inputs

3. Logic Circuit Classification: Sequential Circuit Types • Sequential circuits (also called regenerative circuits) fall into three types: • Bistable • Monostable • Astable • Bistable circuits have two stable operating points and will remain in either state unless perturbed to the opposite state • Memory cells, latches, flip-flops, and registers • Monostable circuits have only one stable operating point, and even if they are temporarily perturbed to the opposite state, they will return in time to their stable operating point • Astable circuits have no stable operating point and oscillate between several states • Ring oscillator

4. Memory Cell: Two-Inverter Basic Bistable Element • A memory cell is comprised of two inverters connected back-to-back, i.e. output of one to input of the other and vice-versa. • The memory cell (or latch) has two stable states where the dc voltage transfer curves cross at the VOH and VOL points, but also exhibits an unstable state. • In actual physical circuits the memory cell will never stay at the unstable point, since any small electrical noise in the circuit will trigger it to one side or the other • In numerical simulation (the circuit may actually remain in the unstable state (assuming no noise source) • The CMOS SRAM cell at the left will either be in state “0” with V01 at GND and V02 at VDD or in state “1” with V01 at VDD and V02 at GND.

5. CMOS SR Latch: NOR Gate Version • The NOR-based SR Latch contains the basic memory cell (back-to-back inverters) built into two NOR gates to allow setting the state of the latch. • If Set goes high, M1 is turned on forcing Q’ low which, in turn, pulls Q high • S=1  Q = 1 • If Reset goes high, M4 is turned on, Q is pulled low, and Q’ is then pulled high • R=1  Q’ = 1 • If both Set and Reset are low, both M1 and M4 are off, and the latch holds its existing state indefinitely • If both Set and Reset go high, both Q and Q’ are pulled low, giving an indefinite state. Therefore, R=S=1 is not allowed • The gate-level symbol and truth table for the NOR-based SR latch are given at left • To estimate Set time, add time to discharge Q’ + time to charge Q (pessimistic result)

6. CMOS SR Latch: NAND Gate Version • A CMOS SR latch built with two 2-input NAND gates is shown at left • The basic memory cell comprised of two back-to-back CMOS inverters is seen • The circuit responds to active low S and R inputs • If S goes to 0 (while R = 1), Q goes high, pulling Q’ low and the latch enters Set state • S=0  Q = 1 (if R = 1) • If R goes to 0 (while S = 1), Q’ goes high, pulling Q low and the latch is Reset • R=0  Q’ = 1 (if S = 1) • Hold state requires both S and R to be high • S = R = 0 if not allowed, as it would result in an indeterminate state

7. Clocked SR Latch: NOR Version • Shown at left is the NOR-based SR latch with a clock added. • The latch is responsive to inputs S and R only when CLK is high • When CLK is low, the latch retains its current state • Timing diagram shows the level-sensitive nature of the clocked SR latch. • Note four times where Q changes state: • When S goes high during positive CLK • On leading CLK edge after changes in S & R during CLK low time • A positive glitch in S while CLK is high • When R goes high during positive CLK

8. Clocked CMOS SR Latch: Implementation • CMOS implementation of clocked NOR-based SR latch shown at left with logic symbol circuit below • Only 12 transistors required • When CLK is low, two series legs in N tree are open and two parallel transistors in P tree are ON, thus retaining state in the memory cell • When CLK is high, the circuit becomes simply a NOR-based CMOS latch which will respond to inputs S and R

9. Clocked CMOS JK Latch: NAND Version • The SR latch has a problem in that when both S and R are high, its state becomes indeterminate • The JK latch shown at left eliminates this problem by using feedback from output to input, such all states in the truth table are allowable • If J = K = 0, the latch will hold its present state • If J = 1 and K = 0, the latch will set on the next positive-going clock edge, i.e. Q = 1, Q’ = 0 • If J = 0 and K = 1, the latch will reset on the next positive-going clock edge, i.e. Q’ = 1 and Q = 0 • If J = K = 1, the latch will toggle on the next positive-going clock edge • Note that in order to prevent the JK Latch above from oscillating continuously during the clock active time, the clock width must be kept smaller than the switching delay time of the latch. Otherwise, several oscillations may occur before the clock goes low again. In practice this may be difficult to achieve.

10. JK Master-Slave Flip-Flop • A Flip-Flop is defined as two latches connected serially and activated with opposite phase clocks • First latch is the Master; Second latch is the Slave • Eliminates transparency, i.e. a change occurring in the primary inputs is never reflected directly to the outputs, since opposite phase clocks are used to activate the M and S latches. • A JK master-slave flip-flop (NOR-based version) is shown below: • The feedback paths occur from Q and Q’ slave outputs to the master inputs gates • does not exhibit any tendency to oscillate when J = K = 1 no matter how long the clock period, since opposite clock phases activate the master and slave latches separately. • The NOR-based version can be done with four CMOS gates, requiring 28 transistors • Can be susceptible to “ones catching”, i.e. a positive glitch in either the J or K input while the CLK is high, which can change the state of the master latch (and the slave latch on next edge)

11. CMOS D-Latch Implementation • A D-latch is implemented, at the gate level, by simply utilizing a NOR-based S-R latch, connecting D to input S, and connecting D’ to input R with an inverter. • When CLK goes high, D is transmitted to output Q (and D’ to Q’) • When CLK goes low, the latch retains its previous state • The D latch is normally implemented with transmission gate (TG) switches, as shown at the left • The input TG is activated with CLK while the latch feedback loop TG is activated with CLK’ • Input D is accepted when CLK is high • When CLK goes low, the input is open-circuited and the latch is set with the prior data D

12. CMOS D-Latch Schematic View and Timing • A schematic view of the D-Latch can be obtained using simple switches in place of the TG’s • When CLK = 1, the input switch is closed allowing new input data into the latch • When CLK = 0, the input switch is opened and the feedback loop switch is closed, setting the latch • Timing diagram: • In order to guarantee adequate time to get correct data at the first inverter input before the input switch opens, the data must be valid for a given time (Tsetup) prior to the CLK going low. • In order to guarantee adequate time to set the latch with correct data, the data must remain valid for a time (Thold) after the CLK goes low. • Violations of Tsetup and Thold can cause metastability problems and chaotic transient behavior.

13. Alternate CMOS D-Latch Implementation • An alternate (preferred) version of the CMOS D-Latch (shown at left) is implemented with two tri-state inverters and a normal CMOS inverter. • Functionally it is similar to the previous chart D-Latch • When CLK is high, the first tri-state inverter sends the inverted input through to the second inverter, while the second tri-state is in its high Z state. • Output Q is following input D • When CLK is low, the first tri-state goes into its high Z state, while the second tri-state inverter closes the feedback loop, holding the data Q and Q’ in the latch.

14. D Register Implementation in CMOS • CMOS implementation of the popular positive edge-triggered D register is shown • Comprised of four transmission gates and five inverters • Operation • Clock = 0: • Master latch is connected to input to receive new D data • Slave latch is holding previous data on output and is isolated from input • Clock = 1: • Master latch stops sampling input, latches up the D data at the positive clock edge, and sends it through to the output Q

15. CMOS Static Latches with Single Phase Clock • Various types of D latch circuit with single phase clocks • (a) shows the use of a weak inverter to allow removal of feedback loop X-gate but retain static latch function • (b) D latch ckt with input inverter buffer • (c) implementation of (b) utilizing tri-state buffer/inverter circuits with clocks at center of tri-state • Alternate schematic of (c) indicating layout convenience due to common tie point at output of tri-state buffers • Clock skew problems can be solved on-chip by using buffering in clock nets • Inverter buffers to generate neg clk • Transmission gate buffers for true clk

16. Construction of D Register (Flip-Flop) in CMOS • Two level-sensitive latches are combined to form a positive edge-triggered register, as is used to build a D register • (a) shows negative level sensitive latch (valid when clock is negative) • (b) shows positive level sensitive latch (valid when clock is positive) • (c) shows positive edge-triggered D register (also called a Flip-Flop) comprised of a negative latch feeding a positive latch • First latch is the Master • Second latch is the Slave • D register timing: • Output Q valid at Tq (clock-to-Q) delay after clock edge • Data must be valid Ts (setup time) prior to clock edge and Th (hold time) after clock edge

17. CMOS D Flip-Flop: Falling Edge-Triggered • Shown below is a D Flip-Flop, constructed by cascading two D-Latch circuits from the previous chart • Master latch is positive level sensitive (receives data when CLK is high) • Slave latch is negative level sensitive (receives data Qm when CLK is low) • The circuit is negative-edge triggered • The master latch receives input D until the CLK falls from high to low, at which point it sets that data in the master latch and sends it through to the output Qs

18. Clocked SR Latch: NAND Version • NAND version of clocked SR latch with active high clock is shown • Circuit is implemented with four NAND gates, not with an AOI or OAI • 16 transistors required • The latch is responsive to S or R only if CLK is high • When CLK is low, the latch retains its present state

19. Timing Definitions CLK Register t D Q t t su hold D DATA CLK STABLE t t c q 2 Q DATA STABLE t

20. V Vi2 V V i o1 1 o 2 A C B V V = = V V i i 2 1 o o 2 1 Positive Feedback: Bi-Stability 1 1 o o V V 5 2 i V 1 o V 5 2 i V

21. CLK D D CLK Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Forcing the state (can implement as NMOS-only) Converting into a MUX

22. Q 0 Q 1 D 1 D 0 CLK Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK

23. Mux-Based Latch

24. Mux-Based Latch NMOS only Non-overlapping clocks

25. Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

26. Master-Slave Register Multiplexer-based latch pair

27. Reduced Clock Load Master-Slave Register

28. Avoiding Clock Overlap X CLK CLK Q A D B CLK CLK (a) Schematic diagram CLK CLK (b) Overlapping clock pairs Need to use non-overlapping clocks f1 and f2 Must be careful about limiting the non-overlapping period

29. ─Cross-Coupled Pairs NOR-based set-reset

30. Cross-Coupled NAND Added clock Cross-coupled NANDs This is not used in datapaths any more,but is a basic building memory cell

31. Storage Mechanisms Dynamic (charge-based) Static CLK D Q CLK

32. Pulse-Triggered LatchesAn Alternative Approach Ways to design an edge-triggered sequential cell: Master-Slave Latches Pulse-Triggered Latch L1 L2 L Data Data D Q D Q D Q Clk Clk Clk Clk Clk

33. Other Latches/Registers: C2MOS “Keepers” can be added to make circuit pseudo-static Clocked CMOS