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Andeshape TM

Andeshape TM. A-ICE Connector. LCM Connector. EBI/X-BUS. LED. Nor Flash. GPIO Push Buttons. SD/MMC. Oscillator. SDRAM. VIRTEX. AHB Connector. MII Connector. Reset Button. Flash. Power On Button. DC-IN Jack. RJ45. Power Switch. UARTs. Audio Phone Jack.

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Andeshape TM

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  1. AndeshapeTM

  2. A-ICE Connector LCM Connector EBI/X-BUS LED Nor Flash GPIO Push Buttons SD/MMC Oscillator SDRAM VIRTEX AHB Connector MII Connector Reset Button Flash Power On Button DC-IN Jack RJ45 Power Switch UARTs Audio Phone Jack ADP-XC5FF676 Main Board Overview

  3. Customerdesign CPUCore NCORE INCTRL Andes Embedded System Platform Block Diagram • AHB bus • Masters • CPU Core • MAC • LCD controller • DMA controller • APB Bridge • Slaves • All device on AHB are slave except N1213 • APB bus • SRAM/SDRAM are sharing the IO pin on address and data • Side Band

  4. ADP-XC5 System Block Diagram

  5. ADP-XC5FF676 Profile • CPU frequency is 80 MHz : N1213; 40MHz : N903 • AHB Clock is 40 MHz • XILINX Virtex5 LX110 • 64MB SDRAM SO-DIMM • 32MB NOR Flash • X-Bus for AIT Chip • 10/100 Ethernet • SD card slot • 2-Digit debug port • AndesICE port • 5 push bottons • 2 UART ports

  6. AndeShape eBIOS booting

  7. Boot procedures • Plug in DC power to main board • Turn power switch to ‘ON’ • Press push-button “SW4”

  8. Diagnostic Main Menu ------------------------------------------------------------------------------ Andes Development Platform Diagnosis Menu, Built@Aug 25 2008 (release: 1.1) CPU: N10 Platform: EVB-AG101 Cache: no cache CPU: 40MHz HCLK: 40MHz ------------------------------------------------------------------------------ ( 1) SDRAM Test ( 2) Timer Test ( 3) DMA Test ( 5) UART Loopback Test ( 6) UART DMA Test ( 9) Watchdog Test (10) Watchdog Reset Test(11) MAC Loopback Test (12) Flash Test (13) SODIMM Sizing (14) SDRAM(bnk1,2) (17) AC97 Test (18) AC97 DMA Test (21) LCD Test (23) Query RTC (24) RTC Alarm Test (25) GPIO Test (55) CLI (67) Set Console's UART (75) Burnin Test (93) Exec Img on LM(I/D) (94) Dhrystone Test (95) Boot Selection (97) CopyImageFromCard (99) Setup Command>>

  9. HW Development Solution

  10. . SW development . AICE debug Download your FPGA design SOC platform with N903 User Define Module AHB Extension Bus ADP-XC5 Development Board ADP-XC5Development Board AHB Extension Bus – Two Leopards Solution

  11. N903 DMA MAC AHB Extension Header User Define Circuit AHB Bus DRAM LCD Uart / SPI AHB Extension Bus – Quick SOC Integration

  12. AHB Basic Protocol

  13. AHB Extension Bus Header

  14. Bidirectional Bus Control • Address Phase • Master issue command • haddr • hwrite • htrans • hsize • hburst • Data Phase • Master/Slave read and write data • hdata • Slave response • Hready • hresp

  15. Reserved External Devices • Ext. AHB Master • Master No. 5 • X_hm5_hbusreq • X_hm5_hgrant • Master No. 6 • X_hm6_hbusreq • X_hm6_hgrant

  16. Reserved External Device • Ext. AHB Slave • Slave No. 13,15,17,18,19,21,22 • X_hs13_hsel, X_hs15_hsel, X_hs17_hsel, X_hs18_hsel, X_hs19_hsel, X_hs21_hsel, X_hs22_hsel • Memory Size : 1MB, 1MB, 1MB, 1MB, 1MB, 256MB, 128MB, • Address Map : 0x90A0_0000, 0x90C0_0000, 0x90E0_0000, 0x90F0_0000, 0x9200_0000, 0xA000_0000, 0xB000_0000

  17. Thank You

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