Flip-Flops Matching of Sequential Circuit

1. Flip-Flops Matching of Sequential Circuit Speaker : Adonis Lin Advisor : Chun-Yao Wang 2007.9.20 Department of Computer Science National Tsing Hua University, Taiwan

2. Outline • Problem Formulation • Research Application • Problem of our work • Probable Resolution • Conclusion • Future Work

3. Problem Formulation • Given • A product machine of two sequential circuits • Two separate circuit space (only same PI) • A sequential circuit • One circuit space (overlap fan in cone of FFs) • Initial state • 0 initial sate , X initial state , specific initial state • Objective • Find flip-flop corresponding or constant flip-flop based on initial state • Exact FFC or Inexact FFC (some may wrong) ?

4. Outline • Problem Formulation • Research Application • Problem of our work • Probable Resolution • Conclusion • Future Work

5. Research Application(1/2) • Need exact FFC • Simplify product machine & sequential circuit • Use equivalence、complement、constant relation of FFs • It can modify delay of circuit (reduce clock skew) • Reduce size of BDD (reachability analysis) • Use Flip-Flop corresponding prevent BDD size from explosion • Map sequential equivalence checking to combinational equivalence checking

6. Research Application(2/2) • Usage of inexact FFC • None We must focus on exact FFC

7. Outline • Problem Formulation • Research Application • Problem of our work • Probable Resolution • Conclusion • Future Work

8. Problem of our work • We can find FFC candidates, but we can not prove it • State reachability problem • If we confirm reachable state space, we can collect exact state Information and then we can find exact FFC (FFC we output must be exist) • FFC can help state reachability analysis, but FFC also need help of state reachability analysis

9. M1 S1 S2 S3 X Y S4 S5 M2 Example • Example (Five state bits in PM) • Flip-flop matching (Underinitial state : S1=1,S2=S3=S4=S5=0) • S1 = S4 * S5 = S2 * S3 • S2 = S4 • S3 = S5 － － － －

10. Run Flow • Step.1 • Set all Flip-Flops to specific initial state • Step.2 • Do < pi – time frame > propagation, it stop when no new FFs can be set by pi • Step.3 • Mark FFs (with value 0 or 1) constant FFs under this initial state • Step.4 • Base on FF = f( pi-time frames ) to find relationship between FFs

11. Equivalent ! Equivalent ! PI Timeframe propagation • Check FFC(2) < Using time frame 2 -- PI > • S1 = • S2 = • S3 = • S4 = • S5 = • FFC(2) = FFC(1) last time frame • S1 = S4 * S5 = S2 * S3 • S2 = S4 • S3 = S5 － － － －

12. Wrong Stop Condition • No new FFs can be set by pi-timeframe • It doesn’t mean no new states will be reached • If some new states still can be reached => Our Information is not exact (Not collect all FFC Info.) • Not exact information => not exact FFC

13. Outline • Problem Formulation • Research Application • Problem of our work • Probable Resolution • Conclusion • Future Work

14. Probable Resolution • SAT solver • Convert sequential circuit to CNF form • Based on above constraint, to prove our FFC candidates => exact FFC • BDD + SAT solver ? • BDD fast but high memory consumption • SAT solver slow but low memory consumption • Sequential ATPG • Find our FFC counter example test pattern • Test pattern does not exist => Exact FFC

15. Outline • Problem Formulation • Research Application • Problem of our work • Probable Resolution • Conclusion • Future Work

16. Conclusion • Two major parts of our research • Find FFC candidates • <PI – Timeframe propagation> collect useful Information • Something else is better ……… • Prove it • SAT solver • Something else is better ………

17. Outline • Problem Formulation • Research Application • Problem of our work • Probable Resolution • Conclusion • Future Work

18. Future Work • Similar paper (ICCAD 2007) • Scalable exploration of functional dependency by interpolation and incremental SAT solving • C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko • Focus on Two major parts of research and find better method or heuristic • Build SAT solver platform to experiment