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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 4 Andy Schellin. Tasks/Workflow. Optimization of Synopsys results Layout Floorplanning , Placement, Routing Improvements. Floorplanning. Best Metric. Cadence Layout. Aspect-Ratio: 3
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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Courseandcontest Resultsof Phase 4 Andy Schellin
Tasks/Workflow • Optimization of Synopsys results • Layout • Floorplanning, Placement, Routing • Improvements
Cadence Layout • Aspect-Ratio: 3 • Timing Driven: high effort • Optimize Design: • Leakage Power Effort: high • Dynamic Power Effort : high • Possible improvements • New order of output pins • Placement by hand in critical areas
Layout with pads • Total Dynamic Power:44,46mW • Cell Leakage Power:6,27mW • 99,73% power loss through pads