STATIC DIGITAL BOARD MAY 12, 2010

1. STATIC DIGITAL BOARD MAY 12, 2010 Rick Sterling

2. Digital Board Status • Engr Model working with PFDP Simulator, TDC, Sweep/Deflector • Minor changes to board circuits and parts for next version • Major change will be implementation of daughter card to carry the FPGA

3. Interconnect Overview • Primary Digital Board Interconnects • LVPS – wtax stackup • Sweep/Deflector – wtax • PFDPU • TDC – 2 x 20 • Anode – Test pulses

4. Digital Schematics Overview

5. Voltage/Hkp Monitoring

6. Control & Test Pulse Outputs

7. Control and Sweep Voltage Outputs

8. Prototype Boards

9. Command & Data Flow (Testing) • Data Flow • Generate start/stop at DG535 • 200 mV pulses to PreAmp • Amplified pulses to TDC • TOF and other data read by FPGA on digital board • Packetized data sent to GSE via IDPU Simulator. • Batch processing and display of data. • Command Flow • GSE sends command to FPGA via IDPU Simulator • FPGA issues appropriate control and goes to commanded configuration. • Example: Set threshold on TDC

10. Development Plan

11. Daughter Card Strategy PLAN: Use Daughter Card to carry the FPGA and JTAG programming connector. This will interface to the mother board with Hypertronics’ HDLP (High Density Low Profile) connectors. RATIONALE: Overall: Minimize risk and maximize flexibility. WHY: Enable use of FLASH based FPGA as long as possible before going to non-reprogrammable fused part. Enable freezing of non FPGA design and layout early in process Enable changing FPGA without changing digital circuit mother board design and layout.

12. Side View of Daughter Card

13. Side View of Daughter Card

14. Overview: Mother and Daughter FPGA CG624: 1.28” x 1.28” HDLP-58: 0.30” x 1.30” JTAG: MicroHeader

15. Next Steps Put the entire STATIC instrument with source into the chamber and do end to end test. Implement and test daughter board interface with digital board.