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Design of Test Access Mechanism for AMBA-Based System-on-a-Chip. Jaehoon Song; Piljae Min; Hyunbean Yi; Sungju Park; “Design of Test Access Mechanism for AMBA-Based System-on-a-Chip” 6-10 May 2007. Adviser : PhD Jin-Hua Hong student : Jun-Yi Wu Date : 2008/12/18. outline. . Abstract
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Design of Test Access Mechanism for AMBA-Based System-on-a-Chip Jaehoon Song; Piljae Min; Hyunbean Yi; Sungju Park; “Design of Test Access Mechanism for AMBA-Based System-on-a-Chip” 6-10 May 2007 Adviser :PhD Jin-Hua Hong student :Jun-Yi Wu Date :2008/12/18
outline • Abstract • Test interfaces for AMBA-based SoC • Establishing dedicated scan-in and out path • Test wrapper • The operation of ATAM
Abstract • A Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-a-Chip (SoC) which adopts an Advanced Microcontroller Bus Architecture (AMBA) bus system. • This architecture has the deficiency of not being able to concurrently shift in and out the structural scan test patterns through the TIC and AMBA bus. • This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. Since scan-in and out operations can be performed simultaneously .
outline • Abstract • Test interfaces for AMBA-based SoC • Establishing dedicated scan-in and out path • Test wrapper • The operation of ATAM
Test interfaces for AMBA-based SoC • The TIC is an interface controller for the functional testing of an AMBA system performing basic AMBA Read/Write transactions as an AMBA bus master.
outline • Abstract • Test interfaces for AMBA-based SoC • Establishing dedicated scan-in and out path • Test wrapper • The operation of ATAM
Establishing dedicated scan-in and out path • TBUS and EBIEXTADDROUT can provide dedicated scan-in and out path, respectively.
Establishing dedicated scan-in and out path(cont.) • A simple OR and MUX logic • TBUS to AHB for transferring the address and test data into embedded cores
Establishing dedicated scan-in and out path(cont.) • shift out the scan test response from the internal AMBA bus to the external output test pins through the HRDATA → EBIDATAOUT → EBIEXTADDROUT path. • The ScanTestMode pin is used to control the normal and test modes
outline • Abstract • Test interfaces for AMBA-based SoC • Establishing dedicated scan-in and out path • Test wrapper • The operation of ATAM
Test wrapper • The (test wrapper)TW consists of PI registers, Address Decoder, Test Clock Generator and MUXs
Test wrapper (cont.) • The address signals from the TIC are decoded by the Address Decoder in TW to select different registers and construct various test paths. • ScnanEnable and CapClkGen signals are produced by the Address Decoder. • The ScanEnable signal enables scan shifting, and the CapClkGen signal notifies the timing of capture clock generation to Test Clock Generator. • Address Decoder selects scan chains, the Test Clock Generator provides the scan shift clock, and single capture clock is triggered by the CapClkGen signal from the Address Decoder.
outline • Abstract • Test interfaces for AMBA-based SoC • Establishing dedicated scan-in and out path • Test wrapper • The operation of ATAM
The operation of ATAM • At first, the address through TBUS selects the target scan chains or PIs, and then scan-in or PI data are written to core through the TBUS → HWDATA path. • POs or scan chains are selected and their values are observed through the HRDATA →EBIDataOut → EBIEXTADDROUT path. • only write transactions to the AMBA bus.