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Pattern Unit s for the Muon DT Status May 2012

Pattern Unit s for the Muon DT Status May 2012. Artur Jutman Testonica Lab + Tallinn University of Technology ESTONIA. PU Prototype Development Status. Action 1: Specification and design proposal – DONE

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Pattern Unit s for the Muon DT Status May 2012

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  1. Pattern Units for the Muon DTStatus May 2012 • ArturJutman • Testonica Lab + Tallinn University of Technology • ESTONIA CMS Upgrade Week – May 22, 2012

  2. PU Prototype Development Status Action 1: Specification and design proposal – DONE Action 2: Design of the SERDES expansion board (SEB) – DONE, expected end of March Action 3: Manufacturing and testing of the SEB prototype – IN PROGRESS, starts May 24 Action 4: Development of the VHDL design for the FPGA – IN PROGRESS, expected end May Action 5: Development of the software – IN PROGRESS, expected mid June Action 6: Integration and prototype validation – IN PROGRESS, expected in June Action 7: Product delivery– end of June CMS Upgrade Week – May 22, 2012

  3. PU Assembly (Sandwich) DC Power Jack 5V SERDES expansion board XEM6010 board LEMO Conn. RJ45 RJ45 USB 2.0 JTAG header (underneath) Status LEDs: “Ready/idle” “Test in progress” “Link fail” Configuration DIP switches (underneath) CMS Upgrade Week – May 22, 2012

  4. Deserializer Board RJ45 Deserializer chips Equalizers LEMO Config Switches Manual Start JTAG CMS Upgrade Week – May 22, 2012

  5. Handling of PUs • PUs controlled by: • Software over USB • Manually by START and RESET buttons • By external START signal • After power on • Transmitter sends default word until START • Receiver waits for START or non-default word • On START • Transmitter sends prepared data • Receiver counts errors • Sources of START signal • External START signal • START button on the Transmitter • START button in the software CMS Upgrade Week – May 22, 2012

  6. Handling of PUs • PUs configuration • Reconfigured by software over USB / JTAG • Configuration stored in the FLASH memory onboard • Configuration includes test patterns and LFSR conf. • Test mode LFSR/normal • Selected by the switch or software • FPGA board selects RX or TX mode • Depending on the type of SERDES board connected CMS Upgrade Week – May 22, 2012

  7. Discussion • Error counter • Reset by Counter Reset button • Any other event to reset it? • 32/64 bit counter – OK? • START signal • All three sources united (ext. START, button, SW) • Casing • Plexiglas plates on top and bottom – OK? CMS Upgrade Week – May 22, 2012

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