Muon DT Upgrade

1. Muon DT Upgrade C. Fernández Bedoya on behalf of DT Upgrade group 15th RDMS CMS Alushta. May 27th 2011

2. C. Fernández Bedoya May 27th, 2011 2 DT Upgrade plans PHASE 1 (2013-2014) * Replacement of theta TRB (Trigger boards) * Relocation of Sector Collector from the cavern (UXC) to the counting room (USC) PHASE 1 following steps (not strictly tighten to LHC shutdowns): * Replacement of DTTF (DT Track Finder) (Trigger Upgrade) * Redesign of the TSC boards (Sector Collector trigger) * Redesign of the ROS boards (Sector Collector read-out) PHASE 2 * Connection with the tracker in the Level-1 trigger system * Replacement of Minicrate electronics? (aging…)

3. C. Fernández Bedoya May 27th, 2011 3 DT Electronics Minicrate Sector Collector DTTF

4. C. Fernández Bedoya May 27th, 2011 4 DT Phase 1: Replacement of theta TRB Minicrate * TRB θ is located inside the Minicrates and generates the trigger in the theta view * It is made of 8 BTIM (Bunch and Track Identifier Modules) also used in the TRB φ DTTF

5. C. Fernández Bedoya May 27th, 2011 5 DT Phase 1: Replacement of theta TRB MOTIVATION * Large number of TRB failures during installation and commissioning of the detector (1%) * Failure rates related to thermal stress of the BTI ASIC bonds (repeated power cycles) * Although a large number of BTI spares were produced, mortality was high during the production stages and we remain with 3% spares * We needed to enlarge the number of BTIM spares: * BTIM technology is obsolete, no more ASICs can be produced * Migration of the BTI algorithm to an FPGA 1 FPGA => 1 BTIM

6. C. Fernández Bedoya May 27th, 2011 6 DT Phase 1: Replacement of theta TRB PRESENT STATUS - R&D has been performed since a few years - One full BTIM has been successfully integrated in one FPGA (good timing) - Functional verification has been performed satisfactorily with test vectors - Radiation tests have been performed in most of the devices and no major problem was found (ProAsic Actel A3PE3000 selected) - Impact of improving the resolution has been studied (no big improvement at present but possibility is open)

7. C. Fernández Bedoya May 27th, 2011 7 DT Phase 1: Replacement of theta TRB 8 FPGAs per TRB PLAN * Produce new TRB to substitute all the TRB θ in MB1 station (60 chambers) * Cannibalize BTIM from replaced boards to enlarge #TRB φ and θspares (recovery efficiency 80-90%) - 2011 Prototype test- 2012 Production + parts procurement- 2013-2014 Bench Test + replacement

8. C. Fernández Bedoya May 27th, 2011 8 DT Electronics On detector Sector Collector UXC USC DTTF

9. C. Fernández Bedoya May 27th, 2011 9 DT Sector Collector • Complex electronics system: • 60 ROS, 60 TSC, VME interface • Contains the second level of: • readout -ROS: • Data merging and data quality monitoring • trigger - TSC: • Multiplexing and sorting sector trigger data Complex electronic system => MAIN TASK is MULTIPLEXING ROS TSC

10. C. Fernández Bedoya May 27th, 2011 10 DT Phase 1: Relocation of SC crate MOTIVATION The motivation is not the physics performance but the fact that aging and other risks may jeopardize detector operation and contribute to an accelerated degradation - Impact of a failure in one SC part compromises a large fraction of the detector - Recovery time can become significantly large (weeks) - Magnetic fields (limited cooling capability) and radiation doses impose important restrictions to the development of a higher performance system - We think relocation of the SC in USC is a necessary change to allow future modifications

11. C. Fernández Bedoya May 27th, 2011 11 DT Phase 1: Relocation of SC crate • Make a “simple” 1 to 1 copper to OF conversion at UXC => CuOF • And back in USC => OFCu Low impact modifications: compatible with present system and with possible future upgrades Present system Proposed upgrade

12. C. Fernández Bedoya May 27th, 2011 12 UXC: CuOF Architecture Input cables from Minicrates Optical Fibers to USC Optimization of mapping to reduce impact of a failure

13. C. Fernández Bedoya May 27th, 2011 13 USC: OFCu Architecture - Rear transition modules to minimize space needed (i.e. allocate Trigger electronics close to the DTTF) => Minimize L1A latency! -Split Trigger and Readout electronics in different locations: * 5 crates with 12 TSC * 5 crates with 12 ROS -Allow maintaining ROS-TSC link for debugging trigger data 9U VME crate * Reliability for 2015-2018 running is improved * Future upgrades are decoupled from LHC shutdowns - Pluggable receivers To be reused for the new ROS and TSC

14. C. Fernández Bedoya May 27th, 2011 14 Optical Fibers Number of fibers to be brought from UXC to USC: Large number of fibers Blowing fibers from CERN EN/EL 72 connector cable 144 connector cable 1. 2. 3. * Installation of the fibers in 2013-2014 * DETAILS AND PLANNING TO BE REVIEWED WITH TECHNICAL COORDINATION

15. C. Fernández Bedoya May 27th, 2011 15 DT Upgrade: Phase 2 DISCLAIMER • * All of our Phase 1 upgrades are focused on technical reasons • * LHC 2010 has proven that DT performs very satisfactorily • * It is a wonderful and unique detector: • Although based on drift tubes (drift time of 400 ns), it has proven from the very beginning to provide a robust, efficient, pure trigger with synchronization and timing information with uncertainty well below 1 ns. • Goal for Phase 2: • * Multiple scattering limits pt resolution in muon system • * Priority at higher luminosity: • -reduce low momentum muon feedthrough L1: Increasing threshold not very effective High Level Trigger (SW) Big improvement when Tracker is used

16. C. Fernández Bedoya May 27th, 2011 16 DT Upgrade: Phase 2 How to improve pt resolution Associate Muon track with LV1 Track Trigger primitives provided by upgraded Tracker: -Stubs from Stacked Layers or Cluster Width or… anything else depending on what will be the Tracker architecture At present simulations have been done for the Long barrel Tracker geometry but they could be applied to other designs under study Matching window

17. C. Fernández Bedoya May 27th, 2011 17 DT Phase 2: Barrel Algorithm * Associate φ and θ muon trigger primitives within each muon station (before track finding) * Delete duplicates and order by quality rank * Extrapolate to tracker layers * Define size of matching region on the base of the muon primitive position and transverse momentum * Create a list of tracker objects (hits/stubs/tracklets/tracks) found inside the search region, match to filter low momentum tracks * Recompute transverse momentum combining associated objects

18. C. Fernández Bedoya May 27th, 2011 18 DT Phase 2: Extrapolation to the tracker Linear.. hardware oriented algorithm

19. C. Fernández Bedoya May 27th, 2011 19 DT Phase 2: Transverse momentum resolution * Several combinations compared for Barrel * There is a large dependence on lever arm: - Vertex constrain has a big impact but… - DT+2 internal stubs already useful to improve resolution

20. C. Fernández Bedoya May 27th, 2011 20 DT Upgrade: Summary * TRB replacement and SC relocation schedule was advanced to 2013 in view of LHC shutdown plans => Schedule in general is very tight, but hopefully doable * Feasibility studies regarding different parts of the project are evolving well * DT Upgrade group is short in manpower, both for Phase 1 and for Phase 2 * The strategy is to improve as much as possible muon system for Phase 1 in view of further improvements for Phase 2: Phase 1 upgrade project is fully compatible with further improvements * Enhanced pt resolution allow big improvement in trigger rate control: algorithm defined, further work on going.

21. BACK-UP

22. C. Fernández Bedoya May 27th, 2011 22 DT Phase 1: Fibers layout * Space available for routing the fibers is tight but existing * Passing of connectorized fiber and patch panels requirements imposes constrains on the fiber selection * Latency of trigger chain is also an important concern

23. C. Fernández Bedoya May 27th, 2011 23 DT Phase 1: Integration in USC Blowing technique patch panels Structured fibers patch panels • Long list of tasks: • - Optimal arrangement of fibers and patch panels • - Choice of the optimal form factor • Optimization of the trigger chain latency • - Allocation of the crates in USC • Power dissipation and cooling capability

27. C. Fernández Bedoya May 6th, 2011 27 DT Phase 1: Replacement of theta TRB F. Montecassiano PRESENT STATUS * They have successfully integrated one full BTIM in one FPGA (4 full BTI inside an Actel ProAsic3 A3PE300) => 8 FPGAs per TRB * Radiation tests have been performed in most of the devices and no major problem was found: - FPGAs Actel A3PE3000 (8 per board) - IC MAX4375 current-sense supervisor (1 per board) - IC DS18S20 1-wire digital thermometer (1 per board) - Power MOSFET PMOS IRF7425 (1 per board) * Pending: -IC DS2450S 1-wire A/D + remote controlled switches (2 per board) -IC LTC3251 charge-pump step-down low noise (8 per board) to be tested with neutrons this summer * Unfortunately it seems that Microsemi/Actel 65nm could be not in time for this project (it would have reduced from 8 FPGAs to 1 FPGA per board) (Samples only available beg. 2012)

28. C. Fernández Bedoya May 27th, 2011 28 DT Phase 1: Redesign of DTTF system * DTTF was designed with wide parallel data links to meet latency requirements: 120 output connectors: 7680 pins 432 input connectors: 27648 pins * Reliability of the system is low * Redesign the DTTF system in a non obsolete standard (i.e. uTCA) that allows fast serial signal distribution through the backplane * At present under Vienna´s responsibility, in close collaboration with DT Need to allow operation of old and new system in parallel => SPLITTING SYSTEM

29. C. Fernández Bedoya April 14th, 2011 29 DT Phase 1: Redesign of DTTF system PRESENT PLAN * Redesign the DTTF system in a non obsolete standard (i.e. uTCA) that allows fast serial signal distribution through the backplane * At present under Vienna´s responsibility * Feasibility studies are on going

30. DT Collaboration: • INFN Legnaro & University of Padova, ITALY • INFN Bologna, ITALY • INFN Torino, ITALY • CIEMAT, SPAIN • RWTH Aachen, GERMANY Also in close collaboration with DT Track Finder (part of CMS Trigger group): • HEPHY, AUSTRIA • UAM, SPAIN

31. C. Fernández Bedoya April 14th, 2011 31 OF input stage In principle, there is enough space below the false floor in S1 USC to recover extra cable lengths (though it depends on the exact racks to be used). Main problem is to allocate the SC crates in S1: -10 SC crates 11U each -To minimize L1A latency, they should be close to DTTF racks (S1D01 and S2D02) -In DT racks at present there is only space to allocate 6 SC crates (and not very close to DTTF)

32. C. Fernández Bedoya April 14th, 2011 32 DT Read-Out System UXC55 USC55 DDU ROS ROB DT CHAMBERS 30 m copper 240 Mbps ~16 Mbps throughput 100 m optical 800 Mbps ~80 Mbps throughput S-LINK64 320 MB/s ~ 200 MB/s throughput • DDU (FED) • 10 DDU => half a wheel • 12 ch/DDU (only half needed) • Data merging • Data quality monitoring • TTS interface • ~ 0.7 kB muon event size/DDU • Chambers • 5 wheels • 60 sectors • 250 chambers • 660 super-layers • 1640 layers • ~172200 channels • Minicrates • 1500 ROB • 128 ch/ROB • Time digitalization (0.7 ns resolution) • 1 µs time window • Sector Collector • 60 ROS • 25 ch/ROS => 1 sector • Data merging • Data quality monitoring • ~ 260 bytes muon event size/ROS

33. C. Fernández Bedoya April 14th, 2011 33 DT Trigger System

34. Cu to OF conversion Present proposal is to make a 1 to 1 channel Cu-OF (Present links are copper based which length cannot be increased without compromising its reliability) Optical fiber 25 @ 240Mbps 25 @ 240 Mbps 32 @ 480Mbps 32 @ 480 Mbps Copper In the tower racks (substituting present SC) • Plus few components for bias setting (DAC) and monitoring. • OF could be extracted from the back of the SC crate • VME interface at tower rack may not be needed • Power can be extracted from present power supplies