H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba, T.Takashima, T.Takahashi, H.Tomita JAXA

1. Front-end circuit with deep-submicron FD-SOIHirokazu Ikedaikeda.hirokazu@jaxa.jpInstitute of space and astronautical scienceJapan aerospace exploration agency H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba, T.Takashima, T.Takahashi, H.Tomita JAXA Y.AraiA, Y.IkegamiA, H.UshirodaA, Y.UnnoA, O.TajimaA, T.TsuboyamaA, S.TeradaA, M.HazumiA, K.HaraB, H.IshinoC, T.KawasakiD, G.VernerE, E.MartinE, H.TajimaF KEKA, U.TsukubaB, TITC, Niigata UD, U. HawaiiE, SLACF 6th FEE meeting @Perugia, Italy

2. Abstract Employing a 0.15-um fully depleted SOI process from OKI, we are developing front-end circuits for radiation detectors in collaboration with JAXA, KEK and related universities. SOI devices are free from parasitic PNPN structure, and, hence, intrinsically immune to the single event latch-ups. Moreover SOI devices are located on a very thin silicon layer,the energy deposit by impinging　particle is relatively small, and, then, the single event upsets and/or single-event transients are manageable with an appropriate design strategy. Utilizing these benefits, space agencies have been employing SOI devices for their spacecrafts. The application area has been, however, virtually restricted in data processing and telecommunications. When designing front-end circuits with the FD-SOI, we can take benefits such as small floating-body effect, superior sub-threshold characteristics and small temperature coefficient as well as common nature of SOI devices, i.e. small parasitic capacitance, low junction leakage, decrease in substrate coupling noise, and reduction of silicon area. In order to confirm these benefits and to identify possible issues concerning front-end circuits with FD-SOI, we have submitted a small design to OKI via the multi-chip project service of VDEC, the university of Tokyo. The design includes charge sensitive preamplifier circuits with exponential and linear decay configurations, and a trans-impedance amplifier with an active feedback configuration. There also included are comparators with a limiting amplifier scheme. The initial test results and future plan for development are presented in this talk. 6th FEE meeting @Perugia, Italy

3. Team organization JEM/ISS Possible application for solar system exploration, and deep-space observation Possible application for Super-B, SLHC, ILC and material science H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba, T.Takashisma, T.Takahashi, H.Tomita JAXA Y.AraiA, Y.IkegamiA, H.UshirodaA, Y.UnnoA, O.TajimaA, T.TsuboyamaA, S.TeradaA, M.HazumiA, K.HaraB, H.IshinoC, T.KawasakiD, G.VernerE, E.MartinE, H.TajimaF KEKA, U.TsukubaB, TITC, Niigata UD, U. HawaiiE, SLACF 6th FEE meeting @Perugia, Italy

4. Contents for talk • Introduction • TEG fabrication • Circuit and operation • Towards radiation-hardness assurance • Conclusion 6th FEE meeting @Perugia, Italy

5. 1. Introduction Entering into late 1990's, the trend curve of a bulk CMOS process tends to go behind the Moore's law, and, hence, the manufactures are eager to find a way to recover development speed. There exists a general trend : Post-scaling technology…..SOI/SOS, strained-Si, 3D-tr, Cu, High-k, Low-k….. SOI CMOS is then revisited to reveal its performance over an existing bulk CMOS; the SOI CMOS eventually shows up as a successor of the CMOS process inheriting well-matured fabrication technologies for a bulk CMOS. ・Full dielectric isolation: Latchup free, Small area ・Low jucntion capacitance: High speed, Low power ・Low leakage, low Vth shift: High Temp. application ・High soft error immunity: Rad-hard application 6th FEE meeting @Perugia, Italy

6. FD-SOI Kink effect Depletion Layer 6th FEE meeting @Perugia, Italy

7. 0.15-um FD-SOI Processed by Oki Elec. Ind. Co., Ltd SOI: 50 nm, BOX: 200 nm, 6”wafer(UNIBONDTM,SOITEC) Vdd: 1.0 V(core)/1.8 V(I/O), Vth: 0.18(n)/-0.25(p) for LVT Metal: 5-layers, Capacitor: MIM Option: Thick metal for inductors 2. TEG fabrication 4,5,6 inch wafer, CMOS/Bipolar 6,8 inch wafer Mass production JAXA/MHI route (0.2 um) c/o K.Hirose VDEC route(0.15 um) VLSI design & education center, The university of Tokyo KEK route (0.15 um W/ pixel implant) c/o Y.Arai Research ISAS, JAXA 6th FEE meeting @Perugia, Italy

8. In order to identify possible issues when applied for analog FE circuits……. 2.4 mm Charge amplifier TOT amplifier-1 TOT amplifier-2 Trans-impedance amplifier 6th FEE meeting @Perugia, Italy

9. 3. Circuit and operation nMOS (LVT) input Id=100-500 uA W/L=5/0.5 M=360 Cox*W*L=12.5 pF gm= 11.5 mS 6th FEE meeting @Perugia, Italy

10. Short decay Long decay Chain1 The leakage current of the FB circuit determines the slowest decay. 6th FEE meeting @Perugia, Italy

11. Good dynamic range 500 mV 200 mV Noise slope is too large! nchl,pchl nchv,pchv Shot noise dominant Adjustment to balance leakage current 6th FEE meeting @Perugia, Italy

12. 6th FEE meeting @Perugia, Italy

13. 4 fC 40 fC Chain2 6th FEE meeting @Perugia, Italy

14. Pulse width is sensitive to the leakage current associated with the ESD pad! The leakage current is adjusted by moving the VSS voltage for the ESD pad. 18 6th FEE meeting @Perugia, Italy

15. Small overshoot 4 fC 40 fC Chain3 Small overshoot as expected 6th FEE meeting @Perugia, Italy

16. Large dynamic range 6th FEE meeting @Perugia, Italy

17. -8 fC 8 fC Chain4 D/A interference is very severe. 6th FEE meeting @Perugia, Italy

18. 4. Towards radiation-hardness assurance Total dose:radiation hard? Not necessarily the case for gate edge and/or BOX. H-gate, Enclosed gate: ready to use Double gate: No effect from BOX Single event(SEU,SET): radiation hard? Not necessarily the case. TCAD　simulation is in progress 6th FEE meeting @Perugia, Italy

19. As a first step….. DUT DUT 6th FEE meeting @Perugia, Italy

20. 5. Conclusion • FD-SOI　analog front-end circuits are examined under a joint effort • of JAXA , KEK and related institutes as a part of the SOI-pixel detector • development and/or future solar system/deep-space exploration. • The FD-SOI TEG circuits are proved to work even with very low • Vdd voltage thanks to stable low threshold transistors. • 3) Minor issues are identified, and fixed to be submitted to the second • MPW run. • Radiation hardness is still an issue to be examined carefully in terms • of total dose and single event. • 5) Road-map for the SOI technology is on the way of the post-scaling • technology, which conforms with application in a harsh environment • in space and high energy physics. 6th FEE meeting @Perugia, Italy