Signal and Power Integrity ALICE Common Readout receiver card (CRORC)

1. Signal and Power IntegrityALICE Common Readout receiver card (CRORC) Csaba SOOSPH-ESE-BE

2. Introduction • ALICE CRORC intro • Signal Integrity simulations • DDR3 interface • High-speed signals (not shown here) • Power Delivery Network analysis • Pre-layout studies • Post-layout simulations ALICE CRORC SI and PI Simulations

3. ALICE Common Readout Receiver Card Designed by IRI, Frankfurt Uni. and Cerntech Ltd., Budapest, Hungary LPC FMC 3 x QSFP 24 differential pairs6 Gbit/s PCIe Gen2 x8 16 differential pairs5 Gbit/s Power supply: 3.3V, 2.5V, 1.5V, 1.2V, 1.05V, 0.75V 2 x DDR3 SO-DIMM ALICE CRORC SI and PI Simulations (too) Many single-ended lines

4. DDR3 Module Interface • Data group: data strobe and complement, data mask, data and check bits • Address and command group: bank addresses, addresses and command inputs • Control group: chip select, clock enable, on-die termination and reset • Clock group: differential clocks • Fly-by routing topology with termination ALICE CRORC SI and PI Simulations

5. DDR3 Simulation Steps • Clock to Control and Command/Address (CCA) • Calculates the skew • Clock to Strobe • Calculates delays inherent to Fly-by routing • Data Read/Write • Verifies setup/hold timing based on CtoS results • Takes into account write leveling ALICE CRORC SI and PI Simulations

6. Design flow – HyperLynx HyperLynxLineSim “what-if” S-parametersTime-domain waveformsTiming reportsetc. Layout Toole.g. Altium HyperLynxBoardSim Boarddesigner Layoutdesigner Models ALICE CRORC SI and PI Simulations

7. HyperLynx Multi-board Project CRORC Connector(model?) DDR3Modules ALICE CRORC SI and PI Simulations

8. DDRx Simulation Wizard ALICE CRORC SI and PI Simulations

9. DDR3 Simulation Results - Reports ALICE CRORC SI and PI Simulations

10. DDR3 Simulation Results - Waveforms • Waveforms can be saved during simulation for post-simulation analysis Example: DDR3 address (ADDR0) Delay due to fly-by routingtopology ALICE CRORC SI and PI Simulations

11. Waveform analysis Example: DDR3 address (ADDR0) Setup/Hold time ALICE CRORC SI and PI Simulations

12. HyperLynx Multi-board Project CRORC Connector(model?) DDR3Modules ALICE CRORC SI and PI Simulations

13. CRORC DDR3 Simulation Challenges • 2 SO-DIMM modules attached on independent memory I/F • Different module configurations (Single/Dual-rank) • 4, 8 or 16 memory chips (loads) per module • 3 configurations were investigated (SR4, SR8, DR16) • Should be minimized • 3 corners (slow, typical, fast) • 2 x 3 x 3 = 18 runs per simulation steps ! (CCA, CtoS, DW/R) • Each of them requiring many steps producing 100’s of files • Analysis becomes overwhelming • Even though HyperLynx does automatic screening of failures ALICE CRORC SI and PI Simulations

14. Lessons learned • Understanding DDR3 operation is important • DDR3 simulation and post-simulation analysis can take a lot of time – try to reduce the number of different options • HyperLynx batch-mode DDRx simulation is a GREAT help • However, some issues (bugs ?) were found; some of them were not resolved • Some References: • Xilinx WP420 white paper • Micron TN-41-08 technical note Odd delay on DQS3 and DQS4 leadingto failure in CtoS simulation ALICE CRORC SI and PI Simulations

15. PDN Simulation Flow • Pre-layout • Define stack-up (must take into account SI too) • Estimate power consumption (FPGA tools, other…) • Calculate target impedances • Estimate decoupling • Post-layout • Verify decoupling • Simulate DC drop and current density ALICE CRORC SI and PI Simulations

16. PDN Target Impedance Since I(f) is usually not know, we have to use the peak transient current (it is not the peak current!). Zplane Vdd VRM IC ALICE CRORC SI and PI Simulations

17. Plane Impedance Regions • Where is the region of interest ? VRM + Bulk capacitors Board-level PDN design IC package, Chip capacitance ALICE CRORC SI and PI Simulations

18. Decoupling Capacitors Decoupling performance is defined by parasitics: - ESR, ESL - package, mounting HyperLynx quick analysis result ALICE CRORC SI and PI Simulations

19. Top vs. bottom Mounting Bottom Top BottomTop ALICE CRORC SI and PI Simulations

20. Laminate thickness • Thinner laminate helps to reduce the impedance, but watch out for anti-resonance (Cplane + decoupling inductance) Anti-resonance Thinner laminate ALICE CRORC SI and PI Simulations

21. CRORC Power Distribution Network VCC 3.3V VTTVREF VCCINT MGTAVCC VTTVREF MGT 1.5V VCC 2.5V • 16-layer board • 6 ground layers • 2 power layers • 8 signal layers VCC 1.5V MGTAVTT ALICE CRORC SI and PI Simulations

22. Post-Layout Simulation • Some of the 220nF caps (-) were replaced with 1uF caps (-) VCCINT Feffective ALICE CRORC SI and PI Simulations

23. DC Voltage Drop VRM FPGA ALICE CRORC SI and PI Simulations

24. DC Current Density ALICE CRORC SI and PI Simulations

25. Conclusion • HyperLynx supports signal and power simulations • Easy to use tool, with smooth learning curve • DDR3 interface simulation is a complex task, but the batch-mode simulation performs lot of tasks automatically • Post-processing could be very time consuming • PDN analysis provides useful input for layout design • Post-layout PDN simulation could reveal problems ALICE CRORC SI and PI Simulations