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Real-Time System-On-A-Chip Emulation

Real-Time System-On-A-Chip Emulation. Introduction Describing SOC Designs System-Level Design Flow SOC Implemantation Paths-Emulation and ASICs Case Study : A 1 Mbps Narrow-Band Transmission System Conclusions. 4.SOC Implemantation Paths-Emulation and ASICs. Berkeley Emulation Engine

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Real-Time System-On-A-Chip Emulation

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  1. Real-Time System-On-A-Chip Emulation

  2. Introduction • Describing SOC Designs • System-Level Design Flow • SOC Implemantation Paths-Emulation and ASICs • Case Study : A 1 Mbps Narrow-Band Transmission System • Conclusions

  3. 4.SOC Implemantation Paths-Emulation and ASICs • Berkeley Emulation Engine • Direct Mapped Designs and the BEE Architecture • BEE Emulation • Prototyping Concepts for BEE Hardware Emulation • Designing for Hardware Emulation • Designing for ASICs

  4. Berkeley Emulation Engine • Provide a large, unified, real-time emulation flatform for data-flow-centric designs • Rapid prototyping • Using an existing H/W framework to speed up design process • Systhesis-based design method • The emulation runs at the same speed as the final product • Design discription can be utilized in emulation environmant and final ASIC implementation • Maintaining cycle-accurate

  5. Direct Mapped Designs and the BEE Architecture 1 • Direct Mapping – top level element already explicitly specity the H/W architecture with cycle-accurate behavior • FPGA and ASIC implementations are functionally same • Suited for high level of parallelism and low-power with stringent perfomance specifications H/W architecture

  6. Direct Mapped Designs and the BEE Architecture 2 • BEE (Berkeley Emulation Engine) • Two-layer Mesh routing architecture • BEE is optimized towords local connectivity • An aggregate of FPGA chips on a PCB • BPU (BEE Processing Unit) emulate system up to 10million ASIC equivalent gates • MPB(Main Processing Board) • 20 Xilinx VertexE2000 • 16Mbyte SRAM (1Mbyte x 16) • Power efficient when ASIC retaregeted

  7. The BEE Main Processing Board

  8. BEE Emulation • SBC :enables a BPU to be connected to Ethernet • SBC 가 20개의 FPGA(MPB) 와 configuration FPGA 를 통해서 연결 • BPU 의 모든기능을 제어 • Programming FPGA • Data read back • Clock domain control • Power management • Thermal management H/W infrastructure and information flow

  9. Prototyping Concepts for BEE Hardware Emulation • Functional and cycle-level emulaton 과 filnal ASIC implementation 은 동등한 과정 • Concept-oriented prototyping • BEE excels in real-time in-circuit verification

  10. Designing for Hardware Emulation • 일반적인 design flow 에 BEE technology mapping • Partitioning for BEE emulator is hard problem • high-level partitioning is left for the user • system-level routing architecture has a profound influence on design • designer has a lot of a priori information on the layout of the design. • Xilinx System Generator and the Integrated Synthesis Environment(ISE) • automatically technology mapping for individual FPGA’s • Virtual components libraries..

  11. Designing for ASICs • ASIC implementation is possible after the design has been evaluated and approved using BEE hardware emulation • Simulink-to-Silicon Hierarchical Automated Flow Tool • virtual components for ASIC’s are in the form of parameterizable Synopsys Module Compiler descriptions. • Frontend • Synopsys synthesis framework • Backend • Cadence tool suite

  12. 5.Case Study : A 1 Mbps Narrow-Band Transmission System • Digital communication circuit are an application domain which is particulary suited for BEE design enviroment • The solid gray blocks are System Generator blocks that have a direct parametrizable hardware implementation • Master clock frequency : 32 MHz.

  13. High-Level Analysis and the Emulation Run

  14. ASIC Implementation • Running the transmitter through the ASIC flow took 56 minutes of processor time on a 400MHz Sun UltraSPARCII • core area is 0.28mm^2 with a utilization factor of 0.34 • estimated maximum clock speed is 100MHz( > 32MHz) • dynamic power is estimated to be 0.611mW and leakage power 0.016mW • ST Microelectronics 0.13µm CMOS process with lowleakage standard cells

  15. 6.Conclusions • high degree of designer productivity and predictable performance. • Hardware emulation • High verification speed • Confidence on the archieved results • Test can be performed with real-world I/O • Performance and functionality verification can be implemented on the emulator • Objective advantages from the designer’s point of view include improved understanding of the overall system and its real-time behavior with the analog portions of the system. Effecively eliminating the simulation speed bottlenecks, automatic testbench generation, and interoperability with other analysis software

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